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AD574AL Datasheet(PDF) 10 Page - Analog Devices |
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AD574AL Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page AD574A REV. B –10– to valid logic levels after the conversion cycle is completed. The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid. If conversion is initiated by a high pulse as shown in Figure 12, the data lines are enabled during the time when R/C is high. The falling edge of R/C starts the next conversion, and the data lines return to three-state (and remain three-state) until the next high pulse of R/C. Figure 12. High Pulse for R/C—Outputs Enabled While R/C High, Otherwise High-Z Table IV. Stand-Alone Mode Timing Symbol Parameter Min Typ Max Units tHRL Low R/C Pulse Width 250 ns tDS STS Delay from R/C 600 ns tHDR Data Valid After R/C Low 25 ns tHL Output Float Delay 150 ns tHS STS Delay After Data Valid 300 1000 ns tHRH High R/C Pulse Width 300 ns tDDR Data Access Time 250 ns Usually the low pulse for R/C stand-alone mode will be used. Figure 13 illustrates a typical stand-alone configuration for 8086 type processors. The addition of the 74F/S374 latches improves bus access/release times and helps minimize digital feedthrough to the analog portion of the converter. Figure 13. 8086 Stand-Alone Configuration INTERFACING THE AD574A TO MICROPROCESSORS The control logic of the AD574A makes direct connection to most microprocessor system buses possible. While it is impos- sible to describe the details of the interface connections for every microprocessor type, several representative examples will be described here. GENERAL A/D CONVERTER INTERFACE CONSIDERATIONS A typical A/D converter interface routine involves several operations. First, a write to the ADC address initiates a conver- sion. The processor must then wait for the conversion cycle to complete, since most ADCs take longer than one instruction cycle to complete a conversion. Valid data can, of course, only be read after the conversion is complete. The AD574A provides an output signal (STS) which indicates when a conversion is in progress. This signal can be polled by the processor by reading it through an external three-state buffer (or other input port). The STS signal can also be used to generate an interrupt upon completion of conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the AD574A is only 35 microseconds) and the processor has other tasks to perform during the ADC conversion cycle. Another possible time-out method is to assume that the ADC will take 35 microseconds to convert, and insert a sufficient number of “do-nothing” instructions to ensure that 35 microseconds of processor time is consumed. Once it is established that the conversion is finished, the data can be read. In the case of an ADC of 8-bit resolution (or less), a single data read operation is sufficient. In the case of convert- ers with more data bits than are available on the bus, a choice of data formats is required, and multiple read operations are needed. The AD574A includes internal logic to permit direct interface to 8-bit or 16-bit data buses, selected by connection of the 12/8 input. In 16-bit bus applications (12/8 high) the data lines (DB11 through DB0) may be connected to either the 12 most significant or 12 least significant bits of the data bus. The re- maining four bits should be masked in software. The interface to an 8-bit data bus (12/8 low) is done in a left-justified format. The even address (A0 low) contains the 8 MSBs (DB11 through DB4). The odd address (A0 high) contains the 4 LSBs (DB3 through DB0) in the upper half of the byte, followed by four trailing zeroes, thus eliminating bit masking instructions. It is not possible to rearrange the AD574A data lines for right justified 8-bit bus interface. Figure 14. AD574A Data Format for 8-Bit Bus SPECIFIC PROCESSOR INTERFACE EXAMPLES Z-80 System Interface The AD574A may be interfaced to the Z-80 processor in an I/O or memory mapped configuration. Figure 15 illustrates an I/O or mapped configuration. The Z-80 uses address lines A0–A7 to decode the I/O port address. An interesting feature of the Z-80 is that during I/O operations a single wait state is automatically inserted, allowing the AD574A to be used with Z-80 processors having clock speeds up to 4MHz. For applications faster than 4 MHz use the wait state generator in Figure 16. In a memory mapped configuration the AD574A may be interfaced to Z-80 processors with clock speeds of up to 2.5 MHz. |
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