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AD7228ACR Datasheet(PDF) 2 Page - Analog Devices |
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AD7228ACR Datasheet(HTML) 2 Page - Analog Devices |
2 / 8 page REV. A –2– AD7228A–SPECIFICATIONS (VDD = 10.8 V to 16.5 V; VSS = –5 V 10%; GND = 0 V; VREF = +2 V to +10 V 1; R L = 2 k Ω, C L = 100 pF unless otherwise noted.) All specifications TMIN to TMAX unless otherwise noted. 5Sample tested at 25 °C to ensure compliance. 6The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter. Specifications subject to change without notice. (VDD = +15 V 10%, VSS; = GND = 0 V; VREF = +10 V, RL = 2 k Ω, C L = 100 pF unless otherwise noted.) AII specifications TMIN to TMAX unless otherwise noted. DUAL SUPPLY BC T U Parameter Version 2 Version Version Version Units Conditions/Comments STATIC PERFORMANCE Resolution 8 8 8 8 Bits Total Unadjusted Error 3 ± 2 ± 1 ± 2 ± 1 LSB max VDD = +15 V ± 10%, VREF = +10 V Relative Accuracy ± 1 ± 1/2 ± 1 ± 1/2 LSB max Differential Nonlinearity ± 1 ± 1 ± 1 ± 1 LSB max Guaranteed Monotonic Full-Scale Error 4 ± 1 ± 1/2 ± 1 ± 1/2 LSB max Typical tempco is 5 ppm/ °C with V REF = +10 V Zero Code Error @ 25 °C ± 25 ± 15 ± 25 ± 15 mV max Typical tempco is 30 µV/°C TMIN to TMAX ± 30 ± 20 ± 30 ± 20 mV max Minimum Load Resistance 2 2 2 2 k Ω min VOUT = +10 V REFERENCE INPUT Voltage Range 1 2 to 10 2 to 10 2 to 10 2 to 10 V min/V max Input Resistance 2 2 2 2 k Ω min Input Capacitance 5 500 500 500 500 pF max Occurs when each DAC is loaded with all 1s. AC Feedthrough –70 –70 –70 –7 0 dB typ VREF = 8 V p-p Sine Wave @ 10 kHz DIGITAL INPUTS Input High Voltage, VINH 2.4 2.4 2.4 2.4 V min Input Low Voltage, VINL 0.8 0.8 0.8 0.8 V max Input Leakage Current ± 1 ± 1 ± 1 ± 1 µA max VIN = 0 V or VDD Input Capacitance 5 8 8 8 8 pF max Input Coding Binary Binary Binary Binary DYNAMIC PERFORMANCE 5 Voltage Output Slew Rate 2 2 2 2 V/ µs min Voltage Output Settling Time Positive Full-Scale Change 5 5 5 5 µs max VREF = +10 V; Settling Time to ± 1/2 LSB Negative Full-Scale Change 5 5 5 5 µs max VREF = +10 V; Settling Time to ± 1/2 LSB Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. VREF = 0 V; WR = VDD Digital Crosstalk 6 50 50 50 50 nV secs typ Code transition all 0s to all 1s. VREF = +10 V; WR = 0 V POWER SUPPLIES VDD Range 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max For Specified Performance VSS Range –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max For Specified Performance IDD Outputs Unloaded; VIN = VINL or VINH @ 25 °C 16 16 16 16 mA max TMIN to TMAX 20 20 22 22 mA max ISS Outputs Unloaded; VIN = VINL or VINH @ 25 °C 14 14 14 14 mA max TMIN to TMAX 18 18 20 20 mA max SINGLE SUPPLY STATIC PERFORMANCE Resolution 8 8 8 8 Bits Total Unadjusted Error 3 ± 2 ± 1 ± 2 ± 1 LSB max Differential Nonlinearity ± 1 ± 1 ± 1 ± 1 LSB max Guaranteed Monotonic Minimum Load Resistance 2 2 2 2 k Ω min VOUT = +10 V REFERENCE INPUT Input Resistance 2 2 2 2 k Ω min Input Capacitance 5 500 500 500 500 pF max Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS As per Dual Supply Specifications DYNAMIC PERFORMANCE 5 Voltage Output Slew Rate 2 2 2 2 V/ µs min Voltage Output Settling Time Positive Full-Scale Change 5 5 5 5 µs max Settling Time to ±1/2 LSB Negative Full-Scale Change 7 7 7 7 µs max Settling Time to ±1/2 LSB Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. VREF = 0 V; WR = VDD Digital Crosstalk 6 50 50 50 50 nV secs typ Code transition all 0s to all 1s. VREF = +10 V, WR = 0 V POWER SUPPLIES VDD Range 13.5/16.5 13.5/16.5 13.5/16.5 13.5/16.5 V min/V max For Specified Performance IDD Outputs Unloaded; VIN = VINL or VINH @ 25 °C 16 16 16 16 mA max TMIN to TMAX 20 20 22 22 mA max NOTES 1V OUT must be less than VDD by 3.5 V to ensure correct operation. 2Temperature ranges are as follows: B, C Versions; –40 °C to +85°C T, U Versions; –55 °C to +125°C 3Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. 4Calculated after zero code error has been adjusted out. |
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