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Motorola TMOS Power MOSFET Transistor Device Data

Designer's™ Data Sheet

TMOS V™

Power Field Effect Transistor

D2PAK for Surface Mount

P–Channel Enhancement–Mode Silicon Gate

TMOS V is a new technology designed to achieve an on–resis-

tance area product about one–half that of standard MOSFETs. This

new technology more than doubles the present cell density of our

50 and 60 volt TMOS devices. Just as with our TMOS E–FET

designs, TMOS V is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and

power motor controls, these devices are particularly well suited for

bridge circuits where diode speed and commutating safe operating

areas are critical and offer additional safety margin against

unexpected voltage transients.

New Features of TMOS V

• On–resistance Area Product about One–half that of Standard

MOSFETs with New Low Voltage, Low RDS(on) Technology

• Faster Switching than E–FET Predecessors

Features Common to TMOS V and TMOS E–FETS

• Avalanche Energy Specified

• IDSS and VDS(on) Specified at Elevated Temperature

• Static Parameters are the Same for both TMOS V and TMOS E–FET

• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,

Add T4 Suffix to Part Number

Rating

Symbol

Value

Unit

Drain–to–Source Voltage

VDSS

60

Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ)

VDGR

60

Vdc

Gate–to–Source Voltage — Continuous

VGS

VGSM

± 15

± 25

Vdc

Vpk

Drain Current — Continuous @ 25

°C

°C

ID

ID

IDM

23

15

81

Adc

Apk

Total Power Dissipation @ 25

°C

Derate above 25

°C

Total Power Dissipation @ TA = 25°C (1)

PD

90

0.60

3.0

Watts

W/

°C

Operating and Storage Temperature Range

TJ, Tstg

– 55 to 175

°C

Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 23 Apk, L = 3.0 mH, RG = 25 Ω)

EAS

794

mJ

Thermal Resistance — Junction to Case

R

θJC

R

θJA

R

θJA

1.67

62.5

50

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

″ from Case for 10 seconds

TL

260

°C

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Order this document

by MTB23P06V/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

TMOS POWER FET

23 AMPERES

60 VOLTS

RDS(on) = 0.120 OHM

Motorola Preferred Device

D

S

G

TM

MTB23P06V

CASE 418B–02, Style 2

D2PAK

© Motorola, Inc. 1996