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MCIMX515DJM8C Datasheet(PDF) 5 Page - Freescale Semiconductor, Inc |
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MCIMX515DJM8C Datasheet(HTML) 5 Page - Freescale Semiconductor, Inc |
5 / 202 page Features i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor 5 2Features The i.MX51 processor contains a large number of digital and analog modules that are described in Table 2. Table 2. i.MX51 Digital and Analog Modules Block Mnemonic Block Name Subsystem Brief Description 1-WIRE 1-Wire Interface Connectivity Peripherals 1-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example: Dallas DS2502. ARM Cortex™-A8 ARM Cortex™-A8 Platform ARM The ARM Cortex™-A8 Core Platform consists of the ARM Cortex™-A8 processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains the Level 2 Cache Controller, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, and a 256 Kbyte L2 cache. The platform also contains an Event Monitor and Debug modules. It also has a NEON co-processor with SIMD media processing architecture, register file with 32 × 64-bit general-purpose registers, an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating point execute pipeline (FADD, FMUL), load/store and permute pipeline and a Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3). Audio Subsystem Audio Subsystem Multimedia Peripherals The elements of the audio subsystem are three Synchronous Serial Interfaces (SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX). See the specific interface listings in this table. AUDMUX Digital Audio Mux Multimedia Peripherals The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The AUDMUX has seven ports (three internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports. CCM GPC SRC Clock Control Module Global Power Controller System Reset Controller Clocks, Resets, and Power Control These modules are responsible for clock and reset distribution in the system, and also for system power management. The modules include three PLLs and a Frequency Pre-Multiplier (FPM). CSPI-1, eCSPI-2 eCSPI-3 Configurable SPI, Enhanced CSPI Connectivity Peripherals Full-duplex enhanced Synchronous Serial Interface, with data rate up to 66.5 Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. CSU Central Security Unit Security The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX51 platform, and for sharing security information between the various security modules. The Security Control Registers (SCR) of the CSU are set during boot time by the High Assurance Boot (HAB) code and are locked to prevent further writing. Debug System Debug System System Control The Debug System provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). Real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, cross-system triggers, counters, and sequencers. |
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