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ADSP-21061LKB-160 Datasheet(PDF) 4 Page - Analog Devices |
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ADSP-21061LKB-160 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 52 page  Rev. D | Page 4 of 52 | May 2013 ADSP-21061/ADSP-21061L Single-Cycle Fetch of Instruction and Two Operands The ADSP-21061 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro- gram memory (PM) bus transfers both instructions and data (Figure 1 on Page 1). With its separate program and data mem- ory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-21061 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing. Data Address Generators with Hardware Circular Buffers The ADSP-21061’s two data address generators (DAGs) imple- ment circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21061 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. Circular buffers can start and end at any mem- ory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21061 can conditionally execute a multiply, an add, a subtract, and a branch, all in a single instruction. MEMORY AND I/O INTERFACE FEATURES The ADSP-21061 processors add the following architectural features to the SHARC family core. Dual-Ported On-Chip Memory The ADSP-21061 contains one megabit of on-chip SRAM, orga- nized as two blocks of 0.5M bits each. Each bank has eight 16-bit columns with 4k 16-bit words per column. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller. The dual- ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle (see Figure 4 for the ADSP-21061 memory map). On the ADSP-21061, the memory can be configured as a maxi- mum of 32k words of 32-bit data, 64k words for 16-bit data, 16k words of 48-bit instructions (and 40-bit data) or combinations of different word sizes up to 1 megabit. All the memory can be accessed as 16-bit, 32-bit, or 48-bit. A 16-bit floating-point storage format is supported, which effec- tively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit float- ing-point formats is done in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the ADSP-21061’s external port. Off-Chip Memory and Peripherals Interface The ADSP-21061’s external port provides the processor’s inter- face to off-chip memory and peripherals. The 4-gigaword off- chip address space is included in the ADSP-21061’s unified address space. The separate on-chip buses—for program mem- ory, data memory, and I/O—are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. The on-chip Super Har- vard Architecture provides three-bus performance, while the off-chip unified address space gives flexibility to the designer. Addressing of external memory devices is facilitated by on-chip decoding of high order address lines to generate memory bank select signals. Separate control lines are also generated for sim- plified addressing of page-mode DRAM. The ADSP-21061 provides programmable memory wait states and external mem- ory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold, and disable time requirements. Host Processor Interface The ADSP-21061’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with lit- tle additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the processor are supported. The host interface is accessed through the ADSP-21061’s exter- nal port and is memory-mapped into the unified address space. Two channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the ADSP-21061’s external bus with the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the internal memory of the ADSP-21061, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands. DMA Controller The ADSP-21061’s on-chip DMA controller allows zero- overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. |
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