S1C33E07

CMOS 32-bit Application Specific Controller

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32-bit RISC CPU-Core Optimized for SoC (EPSON S1C33 PE)

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Built-in 8KB RAM

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SDRAM Controller with Burst Control

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Generic DMA Controller (HSDMA/IDMA)

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6-ch. PWM Control Timer/Counter

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Supports Several Interfaces

SIO with FIFO (IrDA1.0), SPI, I2S and DCSIO

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5-ch. ADC for Analog Input

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Built-in LCD Controller with 12KB IVRAM

DESCRIPTIONS

The S1C33E07 is a high cost performance 32-bit RISC controller for specific applications that require a lot of

general-purpose I/O, a powerful PWM Timer/Counter function, several serial interfaces including USB-FS device

controller, an ADC and a LCD display system, such as middle-low range electronic dictionaries and label writers/printers.

The S1C33E07 consists of a 32-bit RISC CPU-Core, generic DMA controller, USB-FS device controller, PWM control

Timer/Counter, several interfaces (SIO including IrDA1.0, SPI, I2S and DCSIO), ADC, RAM/Shared IVRAM and RTC

implemented by EPSON SoC design technology using 0.18 μm Mixed Analog Low CMOS Process.

FEATURES

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Technology

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0.18 μm AL-4-Layers mixed analog low power CMOS process technology

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CPU

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EPSON original C33 PE 32-bit RISC CPU-Core with AMBA bus optimized for SoC

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Max. 60 MHz operation

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Internal 2-stage pipeline and 4 instruction queues

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Instruction set: 128 instructions (16-bit fixed length)

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Basic instructions are compatible with the S1C33 32-bit RISC Cores.

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Dual AMBA bus system for CPU and LCDC

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Internal Memories

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8KB RAM

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12KB IVRAM (used as general-purpose RAM or VRAM)

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2KB DST RAM (used as general-purpose RAM or IDMA descriptor table RAM)

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Oscillator Circuit / PLL

OSC3 Oscillator Circuit

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Crystal oscillation: 5 MHz min. to 48 MHz max.

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Ceramic oscillation: 5 MHz min. to 48 MHz max.

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External clock input: 5 MHz min. to 48 MHz max.

PLL

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PLL input frequency: 5 MHz min. to 50 MHz max.

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PLL output frequency: 25 MHz min. to 90 MHz max.

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Multiplication rate:

⋅1 ~ ⋅15.

OSC1 Oscillator Circuit

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Crystal oscillation/External clock input: 32.768 kHz typ.

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High Speed Bus (HB) Modules

SRAMC (SRAM Controller)

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25-bit address lines and 8/16-bit selectable data bus

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UP to a 512M-byte (A[24:0]) address space is provided for each chip enable signal.

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Max. 8 chip enable signals are available to connect external devices.

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Programmable bus wait cycle (0 to 7 cycles)

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Supports external wait signals.