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ISL9112IRT7EVAL1Z Datasheet(PDF) 7 Page - Intersil Corporation

Part # ISL9112IRT7EVAL1Z
Description  1.2A High Efficiency Buck-Boost Regulators
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL9112IRT7EVAL1Z Datasheet(HTML) 7 Page - Intersil Corporation

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ISL9110, ISL9112
7
FN7649.2
July 13, 2012
LOGIC INPUTS
ILEAK
Input Leakage
0.05
1
µA
VIH
Input HIGH Voltage
1.4
V
VIL
Input LOW Voltage
0.4
V
Analog Specifications VVIN = VPVIN = VEN = 3.6V, VOUT = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
(Note 9)
MAX
(Note 8)
UNITS
I2C Interface Timing Specification For SCL, and SDA pins, unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
(Note 9)
MAX
(Note 8) UNITS
Cpin
Pin Capacitance
(Note 11)
15
pF
fSCL
SCL Frequency
(Note 11)
400
kHz
tsp
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed (Note 11)
50
ns
tAA
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing VIL, until SDA exits the
VIL to VIH window (Note 11)
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing VIH during a STOP condition, to SDA
crossing VIH during the following START
condition (Note 11)
1300
ns
tLOW
Clock LOW Time
Measured at the VIL crossings (Note 11)
1300
ns
tHIGH
Clock HIGH Time
Measured at the VIH crossings (Note 11)
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge; both
crossing VIH (Note 11)
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing VIL to SCL falling
edge crossing VIH (Note 11)
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the VIL to VIH window, to SCL
rising edge crossing VIL (Note 11)
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing VIH to SDA
entering the VIL to VIH window (Note 11)
0ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing VIH, to SDA rising
edge crossing VIL (Note 11)
600
ns
tHD:STO
STOP Condition Hold Time for Read, or
Volatile Only Write
From SDA rising edge to SCL falling edge; both
crossing VIH (Note 11)
1300
ns
tDH
Output Data Hold Time
From SCL falling edge crossing VIL, until SDA
enters the VIL to VIH window (Note 11)
0ns
tR
SDA and SCL Rise Time
From VIL to VIH (Note 11)
20 + 0.1 x Cb
250
ns
tF
SDA and SCL Fall Time
From VIH to VIL (Note 11)
20 + 0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip (Note 11)
10
400
pF
Rpu
SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF
For Cb = 400pF, max is about 2k
Ω~2.5kΩ
For Cb = 40pF, max is about 15k
Ω~20kΩ
(Note 11)
1k
Ω
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Typical values are for TA = +25°C and VIN = 3.6V.
10. Quiescent current measurements are taken when the output is not switching.
11. ISL9112 only. Limits established by characterization and are not production tested.


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