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ADC128S052CIMTX Datasheet(PDF) 6 Page - Texas Instruments |
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ADC128S052CIMTX Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 25 page  8 9 10 11 12 13 14 15 16 Track Hold Power Up ADD2 ADD1 ADD0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DIN DOUT SCLK CS Control register 1 2 3 4 5 6 7 1 2 3 4 5 6 7 ADD2 ADD1 ADD0 8 DB11 DB10 DB9 Power Down Power Up Track Hold FOUR ZEROS FOUR ZEROS DB1 DB0 ADC128S052 SNAS333D – AUGUST 2005 – REVISED MARCH 2013 www.ti.com ADC128S052 Converter Electrical Characteristics (1) (continued) The following specifications apply for AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, CL = 50pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits(2) Units 50 200 kSPS (min) Sample Rate fS VA = VD = +2.7V to +5.25V Continuous Mode 1000 500 kSPS (max) tCONVERT Conversion (Hold) Time VA = VD = +2.7V to +5.25V 13 SCLK cycles 30 40 % (min) DC SCLK Duty Cycle VA = VD = +2.7V to +5.25V 70 60 % (max) tACQ Acquisition (Track) Time VA = VD = +2.7V to +5.25V 3 SCLK cycles Acquisition Time + Conversion Time Throughput Time 16 SCLK cycles VA = VD = +2.7V to +5.25V tAD Aperture Delay VA = VD = +2.7V to +5.25V 4 ns ADC128S052 Timing Specifications The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 kSPS to 500 kSPS, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits(1) Units tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min) CS Setup Time prior to SCLK Rising tCSS 4.5 10 ns (min) Edge tEN CS Falling Edge to DOUT enabled 5 30 ns (max) DOUT Access Time after SCLK Falling tDACC 17 27 ns (max) Edge DOUT Hold Time after SCLK Falling tDHLD 4 ns (typ) Edge DIN Setup Time prior to SCLK Rising tDS 3 10 ns (min) Edge tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min) tCH SCLK High Time 0.4 x tSCLK ns (min) tCL SCLK Low Time 0.4 x tSCLK ns (min) DOUT falling 2.4 20 ns (max) CS Rising Edge to DOUT High- tDIS Impedance DOUT rising 0.9 20 ns (max) (1) Tested limits are guaranteed to TI's AOQL (Average Outgoing Quality Level). Timing Diagrams Figure 1. ADC128S052 Operational Timing Diagram 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC128S052 |
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