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ADS1015IDGST Datasheet(PDF) 11 Page - Texas Instruments |
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ADS1015IDGST Datasheet(HTML) 11 Page - Texas Instruments |
11 / 33 page 0x7FF0 - FS ¼ 0 ¼ FS InputVoltage(AIN AIN ) - P N 0x7FE0 0x0001 0x0000 0x8000 0xFFF0 0x8010 - FS 2 - 1 11 2 11 FS 2 - 1 11 2 11 ADS1013 ADS1014 ADS1015 www.ti.com SBAS473C – MAY 2009 – REVISED OCTOBER 2009 DATA FORMAT The ADS1013/4/5 digital filter provides some attenuation of high-frequency noise, but the digital The ADS1013/4/5 provide 12 bits of data in binary Sinc filter frequency response cannot completely twos complement format. The positive full-scale input replace an anti-aliasing filter. For a few applications, produces an output code of 7FF0h and the negative some external filtering may be needed; in such full-scale input produces an output code of 8000h. instances, a simple RC filter is adequate. The output clips at these codes for signals that exceed full-scale. Table 4 summarizes the ideal When designing an input filter circuit, be sure to take output codes for different input signals. Figure 13 into account the interaction between the filter network shows code transitions versus input voltage. and the input impedance of the ADS1013/4/5. Table 4. Input Signal versus Ideal Output Code OPERATING MODES INPUT SIGNAL, VIN The ADS1013/4/5 operate in one of two modes: (AINP – AINN) IDEAL OUTPUT CODE(1) continuous conversion or single-shot. In continuous ≥ FS (211 – 1)/211 7FF0h conversion mode, the ADS1013/4/5 continuously +FS/211 0010h perform conversions. Once a conversion has been completed, the ADS1013/4/5 place the result in the 0 0 Conversion register and immediately begins another –FS/211 FFF0h conversion. In single-shot mode, the ADS1013/4/5 ≤ –FS 8000h wait until the OS bit is set high. Once asserted, the bit is set to '0', indicating that a conversion is currently in 1. Excludes the effects of noise, INL, offset, and progress. Once conversion data are ready, the OS bit gain errors. reasserts and the device powers down. Writing a '1' to the OS bit during a conversion has no effect. RESET AND POWER-UP When the ADS1013/4/5 powers up, a reset is performed. As part of the reset process, the ADS1013/4/5 set all of the bits in the Config register to the respective default settings. The ADS1013/4/5 respond to the I2C general call reset command. When the ADS1013/4/5 receive a general call reset, an internal reset is performed as if the device had been powered on. DUTY CYCLING FOR LOW POWER For many applications, the improved performance at low data rates may not be required. For these applications, the ADS1013/4/5 support duty cycling Figure 13. ADS1013/4/5 Code Transition Diagram that can yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ALIASING ADS1013/4/5 in power-down mode with a data rate As with any data converter, if the input signal set to 3300SPS could be operated by a contains frequencies greater than half the data rate, microcontroller that instructs a single-shot conversion aliasing occurs. To prevent aliasing, the input signal every 7.8ms (128SPS). Because a conversion at must be bandlimited. Some signals are inherently 3300SPS only requires about 0.3ms, the bandlimited. For example, the output of a ADS1013/4/5 enter power-down mode for the thermocouple, which has a limited rate of change. remaining 7.5ms. In this configuration, the Nevertheless, they can contain noise and interference ADS1013/4/5 consume about 1/25th the power of the components. These components can fold back into ADS1013/4/5 operated in continuous conversion the sampling band in the same way as with any other mode. The rate of duty cycling is completely arbitrary signal. and is defined by the master controller. The ADS1013/4/5 offer lower data rates that do not implement duty cycling and offer improved noise performance if it is needed. Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS1013 ADS1014 ADS1015 |
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