MC34151, MC33151

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7

the NPN pullup during the negative output transient, power

dissipation at high frequencies can become excessive.

Figures 20, 21, and 22 show a method of using external

Schottky diode clamps to reduce driver power dissipation.

Undervoltage Lockout

An undervoltage lockout with hysteresis prevents erratic

system operation at low supply voltages. The UVLO forces

to the 5.8 V upper threshold. The lower UVLO threshold is

5.3 V, yielding about 500 mV of hysteresis.

Power Dissipation

Circuit performance and long term reliability are

enhanced with reduced die temperature. Die temperature

increase is directly related to the power that the integrated

circuit must dissipate and the total thermal resistance from

the junction to ambient. The formula for calculating the

junction temperature with the package in free air is:

where:

There are three basic components that make up total

power to be dissipated when driving a capacitive load with

respect to ground. They are:

where:

The quiescent power supply current depends on the

supply voltage and duty cycle as shown in Figure 17. The

device’s quiescent power dissipation is:

where:

Outputs

Outputs

D = Output Duty Cycle

The capacitive load power dissipation is directly related

to the load capacitance value, frequency, and Drive Output

voltage swing. The capacitive load power dissipation per

driver is:

where:

f = frequency

When driving a MOSFET, the calculation of capacitive

in this calculation, power MOSFET manufacturers provide

gate charge information on their data sheets. Figure 18

shows a curve of gate voltage versus gate charge for the ON

Semiconductor MTM15N50. Note that there are three

distinct slopes to the curve representing different input

capacitance values. To completely switch the MOSFET

‘on’, the gate must be brought to 10 V with respect to the

required when operating the MOSFET with a drain to source

16

12

8.0

4.0

0

0

40

80

120

160

8.9 nF

2.0 nF

MTM15N50

Figure 18. Gate−To−Source Voltage

versus Gate Charge

The capacitive load power dissipation is directly related to

the required gate charge, and operating frequency. The

capacitive load power dissipation per driver is:

The flat region from 10 nC to 55 nC is caused by the

drain−to−gate Miller capacitance, occurring while the

MOSFET is in the linear region dissipating substantial

amounts of power. The high output current capability of the

MC34151 is able to quickly deliver the required gate charge

for fast power efficient MOSFET switching. By operating

provided to bring the gate above 10 V. This will reduce the

‘on’ resistance of the MOSFET at the expense of higher

driver dissipation at a given operating frequency.

The transition power dissipation is due to extremely short

simultaneous conduction of internal circuit nodes when the

Drive Outputs change state. The transition power

dissipation per driver is approximately:

Switching time characterization of the MC34151 is

performed with fixed capacitive loads. Figure 14 shows that

for small capacitance loads, the switching speed is limited

by transistor turn−on/off time and the slew rate of the

internal nodes. For large capacitance loads, the switching

speed is limited by the maximum output current capability

of the integrated circuit.