NOIV1SN1300A datasheet(5/76 Pages) ONSEMI

Part #	NOIV1SN1300A

Description	VITA 1300 1.3 Megapixel 150 FPS Global Shutter CMOS Image Sensor

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Manufacturer	ONSEMI [ON Semiconductor]

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NOIV1SN1300A, NOIV2SN1300A

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5

Table 5. ELECTRICAL SPECIFICATIONS

Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6 and 7)

Parameter

Description

Min

Typ

Max

Units

Power Supply Parameters - V1-SN/SE LVDS

vdd_33

Supply voltage, 3.3 V

3.0

3.3

3.6

V

Idd_33

Current consumption 3.3 V supply

90

110

130

mA

vdd_18

Supply voltage, 1.8 V

1.6

1.8

2.0

V

Idd_18

Current consumption 1.8 V supply

45

60

75

mA

vdd_pix

Supply voltage, pixel

3.0

3.3

3.6

V

Idd_pix

Current consumption pixel supply

0.8

1.8

2.5

mA

Ptot

Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V

375

475

575

mW

Pstby_lp

Power consumption in low power standby mode. See Silicon Errata

on page 66

50

mW

Popt

Power consumption at lower pixel rates

Configurable

Power Supply Parameters - V2-SN/SE CMOS

vdd_33

Supply voltage, 3.3 V

3.0

3.3

3.6

V

Idd_33

Current consumption 3.3 V supply

70

90

110

mA

vdd_18

Supply voltage, 1.8 V

1.6

1.8

2.0

V

Idd_18

Current consumption 1.8 V supply

4

7

10

mA

vdd_pix

Supply voltage, pixel

3.0

3.3

3.6

V

Idd_pix

Current consumption pixel supply

0.5

1

mA

Ptot

Total power consumption

220

290

360

mW

Pstby_lp

Power consumption in low power standby mode. See Silicon Errata

on page 66

50

mW

Popt

Power consumption at lower pixel rates

Configurable

I/O - V2-SN/SE CMOS (JEDEC- JESD8C-01): Conforming to standard/additional specifications and deviations listed

fpardata

Data rate on parallel channels (10-bit)

62

Mbps

Cout

Output load (only capacitive load)

10

pF

tr

Rise time (10% to 90% of input signal)

2.5

4.5

6.5

ns

tf

Fall time (10% to 90% of input signal)

2

3.5

5

ns

I/O - V1-SN/SE LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed

fserdata

Data rate on data channels

DDR signaling - 4 data channels, 1 synchronization channel;

620

Mbps

fserclock

Clock rate of output clock

Clock output for mesochronous signaling

310

MHz

Vicm

LVDS input common mode level

0.3

1.25

2.2

V

Tccsk

Channel to channel skew (Training pattern allows per channel skew

correction)

50

ps

V1-SN/SE LVDS Electrical/Interface

fin

Input clock rate when PLL used

62

MHz

fin

Input clock when LVDS input used

310

MHz

tidc

Input clock duty cycle when PLL used

40

50

60

%

tj

Input clock jitter

20

ps

fspi

SPI clock rate when PLL used at fin = 62 MHz

10

MHz

V2-SN/SE CMOS Electrical/Interface

fin

Input clock rate

62

MHz

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