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RMLV0416EGSB-4S2 Datasheet(PDF) 10 Page - Renesas Technology Corp |
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RMLV0416EGSB-4S2 Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 15 page RMLV0416E Series R10DS0205EJ0100 Rev.1.00 Page 10 of 13 2014.2.27 Write Cycle (3) (CS1#, CS2 CLOCK) Note 24. tWP is the minimum time to perform a write. A write starts when all of (CS1#), (CS2), (WE#) and (one or both of LB# and UB#) become active. A write is performed during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write ends when any of (CS1#), (CS2), (WE#) or (one or both of LB# and UB#) becomes inactive. CS1# A0~17 tCW OE# WE# I/O0~15 tDH tWC LB#,UB# tBW CS2 Valid address tWR tAW tAS tWP tDW VIH OE# = “H” level tCW tAS *24 Valid Data Valid Data |
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