June 1997

NDP7052 / NDB7052

N-Channel Enhancement Mode Field Effect Transistor

General Description

Features

________________________________________________________________________________

Symbol

Parameter

NDP7052

NDB7052

Units

V

DSS

Drain-Source Voltage

50

V

V

DGR

Drain-Gate Voltage (R

50

V

V

GSS

Gate-Source Voltage - Continuous

±20

V

- Nonrepetitive (t

±40

I

D

Drain Current

- Continuous

75

A

- Pulsed

225

P

D

Total Power Dissipation @ T

150

W

Derate above 25°C

1

W/°C

T

Operating and Storage Temperature Range

-65 to 175

°C

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Case

1

°C/W

Thermal Resistance, Junction-to-Ambient

62.5

°C/W

NDP7052 Rev.B1

75 A, 50 V. R

Critical DC electrical parameters specified at elevated

temperature.

Rugged internal source-drain diode can eliminate the need

for an external Zener diode transient suppressor.

175°C maximum junction temperature rating.

High density cell design for extremely low R

TO-220 and TO-263 (D

and surface mount applications.

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild's proprietary, high cell

density, DMOS technology. This very high density process has

been especially tailored to minimize on-state resistance,

provide superior switching performance, and withstand high

energy pulses in the avalanche and commutation modes.

These

devices

are

particularly

suited

for

low

voltage

applications such as automotive, DC/DC converters, PWM

motor controls, and other battery powered circuits where fast

switching, low in-line power loss, and resistance to transients

are needed.

S

D

G

© 1997 Fairchild Semiconductor Corporation