February 1996

NDS9948

Dual P-Channel Enhancement Mode Field Effect Transistor

General Description

Features

______________________________________________________________________________

Absolute Maximum Ratings

T

Symbol

Parameter

NDS9948

Units

V

DSS

Drain-Source Voltage

-60

V

V

GSS

Gate-Source Voltage

± 20

V

I

D

Drain Current

- Continuous T

(Note 1a)

± 2.3

A

- Pulsed

T

± 10

- Continuous

T

(Note 1a)

± 1.8

P

D

Power Dissipation for Dual Operation

2

W

Power Dissipation for Single Operation

(Note 1a)

1.6

(Note 1b)

1

(Note 1c)

0.9

T

Operating and Storage Temperature Range

-55 to 150

°C

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient

(Note 1a)

78

°C/W

Thermal Resistance, Junction-to-Case

(Note 1)

40

°C/W

NDS9948.SAM

These P-Channel enhancement mode power field effect

transistors are produced using Fairchild's proprietary, high cell

density, DMOS technology. This very high density process has

been especially tailored to minimize on-state resistance, provide

superior switching performance, and withstand high energy

pulses in the avalanche and commutation modes. These

devices are particularly suited for low voltage applications such

as notebook computer power management and other battery

powered circuits where fast switching, low in-line power loss,

and resistance to transients are needed.

-2.3A, -60V. R

High density cell design for low R

High power and current handling capability in a widely

used surface mount package.

Dual MOSFET in surface mount package.

1

5

6

7

8

4

3

2

© 1997 Fairchild Semiconductor Corporation