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NM24Wxx Rev. C.2

Device Addressing

Following a start condition the master must output the address of

the slave it is accessing. The most significant four bits of the slave

address are those of the device type identifier (

see Figure 4). This

is fixed as 1010 for all EEPROM devices.

Slave Addresses (Figure 4)

All Standard IIC protocol EEPROMs use an internal protocol that

defines a PAGE BLOCK size of 2K bits (for Byte addresses 00

through FF). Therefore, address bits A0, A1, or A2 (if designated

'P') are used to access a PAGE BLOCK in conjuction with the Byte

address used to access any individual data byte.

Refer to the following table for Slave Address string details:

Device

A0 A1 A2

Page

Page Block

Blks

Addresses

NM24W02

A

A

A

1 (2K)

(None)

NM24W04

P

A

A

2 (4K)

0 1

NM24W08

P

P

A

4 (8K)

00 01 10 11

NM24W16

P

P

P

8 (16K)

000 001 010 011 100

101 110 111

Note:

A: Refers to a hardware configured Device Address pin.

P: Refers to an internal PAGE BLOCK memory segment

The last bit of the slave address defines whether a write or read

condition is requested by the master. A '1' indicates that a read

operation is to be executed, and a '0' initiates the write mode.

A simple review: After the NM24Wxx recognizes the start condi-

tion, the devices interfaced to the IIC bus wait for a slave address

to be transmitted over the SDA line. If the transmitted slave

address matches an address of one of the devices, the designated

slave pulls the line LOW with an acknowledge signal and awaits

further transmissions.

Device Type

Identifier

Device

Address

1

0

1

0

A2

A1

A0

R/W

(LSB)

NM24W02

Device Type

Identifier

Device

Address

Page

Block Address

1

0

1

0

A2

A1

A0

R/W

(LSB)

NM24W04

Device Type

Identifier

Device

Address

Page

Block Address

1

0

1

0

A2

A1

A0

R/W

(LSB)

NM24W08

Device Type

Identifier

Page

Block Address

1

0

1

0

A2

A1

A0

R/W

(LSB)

NM24W16

DS500074-11