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NM25C160 Rev. D.1

SCK

SI

SO

CS











D0

D1

D2





CS

SI

SO

Write

Op-Code

Byte H

Addr (n)

Byte L

Addr (n)

Data

(n)

Data

(n+1)

Data

(n+2)

Data

(n+3)

Data

(n+15)

. . .





CS

SI

SO

WRSR

Op-Code

SR Data

xxxxBP1BP0xx

DS012402-12

DS012402-13

DS012402-14

A WRITE command requires the following sequence. The CS line

is pulled low to select the device, then the WRITE op-code is

transmitted on the SI line followed by the high order address byte

(A10-A8) and the low order address byte (A7–A0). The leading five

bits in the high order address byte will be ignored. The address is

followed by the data (D7–D0) to be written. Programming will start

after the CS pin is forced back to a high level. Note that the LOW

to HIGH transition of the CS pin must occur during the SCK low time

immediately after clocking in the D0 data bit. See Figure 10.

FIGURE 10. Write Sequence

BP0

SCK

SI

SO

CS





DS012402-15

The READY/BUSY status of the device can be determined by

executing a READ STATUS REGISTER (RDSR) instruction. Bit 0

= 1 indicates that the WRITE cycle is still in progress and Bit 0 =

0 indicates that the WRITE cycle has ended. During the WRITE

programming cycle (Bit 0 = 1) only the READ STATUS REGIS-

TER instruction is enabled.

The NM25C160 is capable of a 16 byte PAGE WRITE operation.

After receipt of each byte of data the four low order address bits

are internally incremented by one. The seven high order bits of the

address will remain constant. If the master should transmit more

than 16 bytes of data, the address counter will “roll over,” and the

previously loaded data will be reloaded. See Figure 11.

FIGURE 11. 16 Byte Page Write

At the completion of a WRITE cycle the device is automatically

returned to the write disable state.

If the device is not WRITE enabled, the device will ignore the

WRITE instruction and return to the standby state when CS is

forced high. A new CS falling edge is required to re-initialize the

serial communication.

WRITE STATUS REGISTER (WRSR): The WRITE STATUS

REGISTER (WRSR) instruction is used to program the non-

volatile status register Bits 2 and 3 (BP0 and BP1). The WRITE

PROTECT (WP) pin must be held high and two separate instruc-

tions must be executed. The chip must first be write enabled via

the WRITE ENABLE instruction and then a WRSR instruction

must be executed.

The WRSR command requires the following sequence. The CS

line is pulled low to select the device and then the WRSR op-code

is transmitted on the SI line followed by the data to be pro-

grammed. See Figure 12.

FIGURE 12. Write Status Register

Note that the first four bits are don’t care bits followed by BP1 and

BP0 then two additional don’t care bits. Programming will start

after the CS pin is forced back to a high level. As in the WRITE

instruction the LOW to HIGH transition of the CS pin must occur

during the SCK low time immediately after clocking in the last don’t

care bit. See Figure 13.

FIGURE 13. Start WRSR Condition

The READY/BUSY status of the device can be determined by

executing a READ STATUS REGISTER (RDSR) instruction. Bit 0

= 1 indicates that the WRSR cycle is still in progress and Bit 0 =

0 indicates that the WRSR cycle has ended.

At the completion of a WRITE cycle the device is automatically

returned to the write disable state.