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Functional Description

DEVICE OPERATION

The six modes of operation of the EPROM are listed in Table 1. It

should be noted that all inputs for the six modes are at TTL levels.

supply must be at 12.75V during the three programming modes,

supply must be at 6.5V during the three programming modes, and

at 3.3V in the other three modes.

Read Mode

The EPROM has two control functions, both of which must be

logically active in order to obtain data at the outputs. Chip Enable

(CE) is the power control and should be used for device selection.

Output Enable (OE) is the output control and should be used to

gate data to the output pins, independent of device selection.

is equal to the delay from CE to output (t

Standby Mode

The EPROM has a standby mode which reduces the active power

dissipation by over 99%, from 50 mW to 0.17 mW. The EPROM

is placed in the standby mode by applying a CMOS high signal to

the CE input. When in standby mode, the outputs are in a high

impedance state, independent of the OE input.

Output Disable

The EPROM is placed in output disable by applying a TTL high

signal to the OE input. When in output disable all circuitry is

enabled, except the outputs are in a high impedance state (TRI-

STATE).

Output OR-Tying

Because the EPROM is usually used in larger memory arrays,

Fairchild has provided a 2-line control function that accommo-

dates this use of multiple memory connections. The 2-line control

function allows for:

1. the lowest possible memory power dissipation, and

2. complete assurance that output bus contention will not

occur.

To most efficiently use these two control lines, it is recommended

that CE be decoded and used as the primary device selecting

function, while OE be made a common connection to all devices

in the array and connected to the READ line from the system

control bus. This assures that all deselected memory devices are

in their low power standby modes and that the output pins are

active only when data is desired from a particular memory device.

Programming

Initially, and after each erasure, all bits of the EPROM are in the

“1’s” state. Data is introduced by selectively programming “0’s”

into the desired bit locations. Although only “0’s” will be pro-

grammed, both “1’s” and “0’s” can be presented in the data word.

The only way to change a “0” to a “1” is by ultraviolet light erasure.

The EPROM is in the programming mode when the V

0.1

µF capacitor be placed across V

suppress spurious voltage transients which may damage the

device. The data to be programmed is applied 8 bits in parallel to

the data output pins. The levels required for the address and data

inputs are TTL.

When the address and data are stable, an active low, TTL program

pulse is applied to the PGM input. A program pulse must be

applied at each address location to be programmed. The EPROM

is programmed with the LV Turbo Programming Algorithm shown

in Figure 1. Each Address is programmed with a series of 50

µs

pulses until it verifies good, up to a maximum of 10 pulses. Most

memory cells will program with a single 50

µs pulse. (The standard

National Semiconductor Algorithm may also be used, but it will

have longer programming time.)

The EPROM must not be programmed with a DC signal applied to

the PGM input.

Programming multiple EPROM in parallel with the same data can

be easily accomplished due to the simplicity of the programming

requirements. Like inputs of the parallel EPROM may be con-

nected together when they are programmed with the same data.

A low level TTL pulse applied to the PGM input programs the

paralleled EPROM.

Program Inhibit

Programming multiple EPROM’s in parallel with different data is

also easily accomplished. Except for CE, all like inputs (including

OE and PGM) of the parallel EPROM may be common. A TTL low

level program pulse applied to an EPROM’s PGM input with CE at

CE input inhibits the other EPROM’s from being programmed.

Program Verify

A verify should be performed on the programmed bits to determine

whether they were correctly programmed. The verify may be

programming and program verify.

AFTER PROGRAMMING

Opaque labels should be placed over the EPROM window to

prevent unintentional erasure. Covering the window will also

prevent temporary functional failure due to the generation of photo

currents.

MANUFACTURER’S IDENTIFICATION CODE

The EPROM has a manufacturer’s identification code to aid in

programming. When the device is inserted in an EPROM pro-

grammer socket, the programmer reads the code and then

automatically calls up the specific programming algorithm for the

part. This automatic programming control is only possible with

programmers which have the capability of reading the code.

The Manufacturer’s Identification code, shown in Table 2, specifi-

cally identifies the manufacturer and device type. The code for the

NM27LV010 is “8F86”, where “8F” designates that it is made by

Fairchild Semiconductor, and “86” designates a 1 Megabit (128k

x 8) part.

The code is accessed by applying 12V

±0.5V to address pin A9.

Address pin A0 is held at V

pins, O0–07. Proper code access is only guaranteed at 25

°C ±

5

°C.