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ADL5375-15-EVALZ Datasheet(PDF) 6 Page - Analog Devices |
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ADL5375-15-EVALZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 36 page ADL5375 Data Sheet Rev. C | Page 6 of 36 Parameter Conditions ADL5375-05 ADL5375-15 Unit Min Typ Max Min Typ Max LO INPUTS LO Drive Level Characterization performed at typical level −6 0 +6 −6 0 +6 dBm Input Return Loss 500 MHz < fLO < 3.3 GHz See Figure 7 and Figure 32 for return loss vs. frequency ≤−10 ≤−10 dB BASEBAND INPUTS Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN I/Q Input Bias Level1 500 1500 mV Absolute Voltage Level1 On Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN 0 1 1 2 V Input Bias Current Current sourcing from each baseband input 41 32 µA Input Offset Current 0.1 0.1 µA Differential Input Impedance 60 100 kΩ Bandwidth (0.1 dB) LO = 1900 MHz, baseband input = 500 mV p-p sine wave 95 80 MHz OUTPUT DISABLE Pin DSOP Off Isolation POUT (DSOP low) − POUT (DSOP high) 84 85 dB DSOP high, LO leakage, LO = 2150 MHz −55 −53 dBm Turn-On Settling Time DSOP high to low (90% of envelope) 220 220 ns Turn-Off Settling Time DSOP low to high (10% of envelope) 100 100 ns DSOP High Level (Logic 1) 2.0 2.0 V DSOP Low Level (Logic 0) 0.8 0.8 V POWER SUPPLIES Pin VPS1 and Pin VPS2 Voltage 4.75 5.25 4.75 5.25 V Supply Current DSOP = low 194 203 mA DSOP = high 126 127 mA 1 The input bias level can vary as long as the voltages on the individual IBBP, IBBN, QBBP, and QBBN pins remain within the specified absolute voltage level. |
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