LTC4305

4305f

4

The

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Guaranteed by design and not subject to test, unless stated

otherwise in the Conditions.

Note 3: The boosted pull-up currents are regulated to prevent excessively

fast edges for light loads. See the Typical Performance Characteristics for

upstream-downstream buffers, the voltage on the other side is regulated

is the offset voltage when the LTC4305 is driving the upstream pin (e.g.,

driving the downstream pin (e.g., SDA1). See the Typical Performance

bus pull-up current.

Note 5: When floating, the ADR0–ADR2 pins can tolerate pin leakage

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ADR0–2 Input High Voltage

●

0.75

V

ADR0–2 Input Low Voltage

●

0.1

V

ADR0–2 Logic Low Input Current

●

–30

–60

–80

µA

ADR0–2 Logic High Input Current

●

30

60

80

µA

ADR0–2 Allowed Input Current

●

±5

±13

µA

SDAIN, SCLIN Input Falling Threshold Voltages

●

1.4

1.6

1.8

V

SDAIN, SCLIN Hysteresis

30

mV

SDAIN, SCLIN Input Current

●

±5

µA

SDA, SCL Input Capacitance

(Note 2)

6

10

pF

SDAIN Output Low Voltage

●

0.2

0.4

V

Maximum SCL Clock Frequency

(Note 2)

400

kHz

Bus Free Time Between Stop/Start Condition

(Note 2)

0.75

1.3

µs

Hold Time After (Repeated) Start Condition

(Note 2)

45

100

ns

Repeated Start Condition Set-Up Time

(Note 2)

–30

0

ns

Stop Condition Set-Up Time

(Note 2)

–30

0

ns

Data Hold Time Input

(Note 2)

–25

0

ns

Data Hold Time Output

(Note 2)

300

600

900

ns

Data Set-Up Time

(Note 2)

50

100

ns

SCL, SDA Fall Times

(Note 2)

20 + 0.1

•

300

ns

Pulse Width of Spikes Suppressed by the

(Note 2)

50

150

250

ns

Input Filter