TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

5

POST OFFICE BOX 655303

POST OFFICE BOX 1443

control and timing (continued)

the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output

data changes on the rising edge of SCLK. This configuration is typically used for multiple devices connected

to a TMS320 DSP.

TLV2542/5

All control is provided using CS (pin 1) on the TLV2542 and TLV2545. The cycle is started on the falling edge

transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing

is similar to the TLV2541, with control via CS only.

TLV2542 channel MUX reset cycle

The TLV2542 uses CS to reset the analog input multiplexer. A short active CS cycle (4 to 7 SCLKs) resets the

MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as in the case for a complete

conversion cycle (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel

(see Figure 4 for timing). One dummy conversion cycle is recommended after power up before attempting to

reset the MUX.

sampling

The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter

has received a high-to-low CS transition (or a high-to-low FS transition for the TLV2541).

conversion

The TLV2541, TLV2542, and TLV2545 complete conversions in the following manner. The conversion is started

after the 16th SCLK falling edge and takes 3.5 μs to complete. Enough time (for conversion) should be allowed

before a rising CS or FS edge so that no conversion is terminated prematurely.

TLV2542 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0

via CS as described in the earlier section and in Figure 4. The input is sampled for 12 SCLKs, converted, and

the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between

samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is

not complete.

The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous

cycle.

timing diagrams/conversion cycles

SCLK

1

2

3

4

5

6

12

13

14

15

16

1

CS

FS

OD8

OD7

OD6

OD5

OD0

SDO

7

OD10

OD11

OD9

Figure 2. TLV2541 Timing: Control via CS (FS = 1)