TMS370Cx8x

8-BIT MICROCONTROLLER

SPNS035B –DECEMBER 1995 – REVISED FEBRUARY 1997

10

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The TMS370C686 device contains 16K bytes of EPROM memory, mapped beginning at location 4000h and

continuing through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical

to reading other internal memory. During programming, the EPROM is controlled by the EPROM control register

(EPCTL). The program EPROM module features include:

–

–

Control register EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01C as shown in Table 6.

–

Reset all programming to the EPROM module is halted

–

Low-power modes

–

13 V not applied to MC

The program ROM consists of 4K bytes of mask-programmable read-only memory. The program ROM is used

for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device

fabrication.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx8x CPU-based device.

There are up to three different actions that can cause the system to reset the device. Two of these actions are

generated internally, while one (RESET pin) is controlled externally. These actions are as follows:

register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 User’s

Guide (literature number SPNU127) for more information.

See the

TMS370 User’s Guide (literature number SPNU127) for more information.

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 User’s Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

for several hundred milliseconds) condition or oscillator failure occurs, or the RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag

(COLD START, SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 7 depicts the reset sources.

† Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments Incorporated, and 7FF4h through 7FF5h along with 7FF8h

through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between

addresses 7FC0h and 7FDFh.