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ABSOLUTE MAXIMUM RATINGS

Recommended Operating Conditions

DISSIPATION RATINGS

(1) (2)

TPS54610

SLVS398F – JUNE 2001 – REVISED APRIL 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

OUTPUT VOLTAGE

PART NUMBER

40

°C to 85°C

Adjustable down to 0.9 V

Plastic HTSSOP (PWP)

TPS54610PWP

(1)

The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54610PWPR). See the application

section of the data sheet for PowerPAD drawing and layout information.

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

TPS54610

VIN, SS/ENA, SYNC

-0.3 V to 7 V

RT

-0.3 V to 6 V

Input voltage range

VSENSE

-0.3 V to 4 V

BOOT

-0.3 V to 17 V

VBIAS, COMP, PWRGD

-0.3 V to 7 V

Output voltage range

PH

-0.6 V to 10 V

PH (transient < 10 ns)

-2 V

PH

Internally Limited

Source current

COMP, VBIAS

6 mA

PH

12 A

Sink current

COMP

6 mA

SS/ENA, PWRGD

10 mA

Voltage differential

AGND to PGND

±0.3 V

Operating virtual junction temperature range

-40

°C to 125°C

Storage temperature

-65

°C to 150°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

MIN

NOM

MAX

UNIT

3

6

V

–40

125

°C

THERMAL IMPEDANCE

PACKAGE

JUNCTION-TO-AMBIENT

POWER RATING

POWER RATING

POWER RATING

28 Pin PWP with solder

18.2

°C/W

3.02 W

2.20 W

28 Pin PWP without solder

40.5

°C/W

2.48 W

1.36 W

0.99 W

(1)

For more information on the PWP package, see TI technical brief, literature number SLMA002.

(2)

Test board conditions:

a.

3 inch x 3 inch, 4 layers, thickness: 0.062 inch

b.

1.5 oz. copper traces located on the top of the PCB

c.

1.5 oz. copper ground plane on the bottom of the PCB

d.

0.5 oz. copper ground planes on the 2 internal layers

e.

12 thermal vias (see Recommended Land Pattern in applications section of this data sheet

(3)

Maximum power dissipation may be limited by over current protection.

2

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