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TMS32C6416DGLZ6E3 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS32C6416DGLZ6E3 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 145 page TMS320C6414, TMS320C6415, TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146N − FEBRUARY 2001 − REVISED MAY 2005 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents reset 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 76 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 76 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 77 . recommended clock and control signal transition behavior 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parameter measurement information 78 . . . . . . . . . . . . . . . input and output clocks 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 84 . . . . . . . . . . . . . . . . . . . . . programmable synchronous interface timing 88 . . . . . . . . synchronous DRAM timing 93 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 107 . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface (HPI) timing 108 . . . . . . . . . . . . . . . . . . . peripheral component interconnect (PCI) timing [C6415 and C6416 only] 113 . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port (McBSP) timing 116 . . . . UTOPIA slave timing [C6415 and C6416 only] 127 . . . . . . timer timing 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) port timing 131 . . . . JTAG test-port timing 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GLZ, ZLZ and CLZ BGA packages (bottom view) 3 . . . . . . . . description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device compatibility 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and CPU (DSP core) diagram 7 . . . . . . . . . . . CPU (DSP core) description 8 . . . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 14 . . . . . . . . . . . . . . . . . . . . . . . EDMA channel synchronization events 27 . . . . . . . . . . . . . . . . interrupt sources and interrupt selector 29 . . . . . . . . . . . . . . . . signal groups description 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multiplexed pins 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging considerations 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device support 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) 69 . . . . . . . . . . . . . . . . . . power-down mode logic 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 74 . . . . . . . . . . . . . EMIF device speed 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootmode 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS146M device-specific data sheet to make it an SPRS146N revision. Scope: Applicable updates to the C64x device family, specifically relating to the C6414, C6415, and C6416 devices, have been incorporated. PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS Global: Added “CLZ” (532-pin plastic BGA, Pb−free bump and Pb−free soldered balls) mechanical package information |
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Similar Description - TMS32C6416DGLZ6E3 |
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