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SN74GTLP1395PWE4 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74GTLP1395PWE4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 24 page www.ti.com FEATURES DGV, DW, OR PW PACKAGE (TOP VIEW) 1Y 1T/C 2Y GND 1OEAB VCC 1A GND 2A 2OEAB 1OEBY 2T/C 2OEBY GND 1B ERC 2B GND VREF BIAS VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DESCRIPTION/ORDERING INFORMATION SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C–JUNE 2001–REVISED JANUARY 2006 • ESD Protection Exceeds JESD 22 • TI-OPC™ Circuitry Limits Ringing on – 2000-V Human-Body Model (A114-A) Unevenly Loaded Backplanes – 200-V Machine Model (A115-A) • OEC™ Circuitry Improves Signal Integrity and – 1000-V Charged-Device Model (C101) Reduces Electromagnetic Interference • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels • Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring • LVTTL Interfaces Are 5-V Tolerant • High-Drive GTLP Outputs (100 mA) • LVTTL Outputs (–24 mA/24 mA) • Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion • Polarity Control Selects True or Complementary Outputs • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load impedance down to 11 Ω. GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT =1.2 Vand VREF = 0.8 V) or GTLP (VTT =1.5 Vand VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI-OPC, OEC are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2001–2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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