SN75061

DRIVER/RECEIVER PAIR WITH SQUELCH

SLLS026C − JANUARY 1987 − REVISED JULY 1990

2−10

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

DLEN at 3 V

50

Ω

DRI at 0 V or 3 V

Generator

(see Note A)

DRDLAJ

5 V

Rext = 62 kΩ

Cext = 100 pF

DATEN

DRO +

DRO −

RL = 100 Ω

Output

CL = 50 pF

(see Note B)

TEST CIRCUIT

VOLTAGE WAVEFORMS

5 V

Output

Input

3 V

0 V

2.3 V

VOL

0.5 V

≈ 5 V

tPZL

tPLZ

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR

≤ 200 kHz, duty cycle ≤ 50%, tr ≤ 6 ns,

tf ≤ 6 ns, ZO = 50 Ω.

B. CL includes probe and jig capacitance.

Figure 4. Test Circuit and Voltage Waveforms for Driver Enable and Disable Time

DLEN at 3 V

50

Ω

DRI

GENERATOR

(see Note A)

DRDLAJ

5 V

Rext = 62 kΩ

Cext = 100 pF

DATEN at 3 V

DRO +

DRO −

RL = 100 Ω

Output

TEST CIRCUIT

VOLTAGE WAVEFORMS

Output

Input

3 V

0 V

2.3 V

VOH

1.5 V

≈ 0 V

CL = 50 pF

(see Note B)

tPZH

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR

≤ 1 MHz, duty cycle ≤ 50%, tr ≤ 6 ns, tf ≤ 6 ns,

ZO = 50 Ω.

B. CL includes probe and jig capacitance.

Figure 5. Test Circuit and Voltage Waveforms for Enable Time From Delay Enable