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SN65HVD255 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65HVD255 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 28 page TXD DTO RXD DTO Thermal Shutdown FAULT GND UV Lockout VCC or VIO µP FAULT Input SN65HVD255 SN65HVD256, SN65HVD257 SLLSEA2C – DECEMBER 2011 – REVISED SEPTEMBER 2013 www.ti.com Undervoltage Lockout The supply pins have undervoltage detection that places the device in protected mode. This protects the bus during an undervoltage event on either the VCC or VRXD supply pins. Table 4. Undervoltage Lockout 5V Only Devices (SN65HVD255 and SN65HVD257) VCC DEVICE STATE BUS OUTPUT RXD GOOD Normal Per Device State and TXD Mirrors Bus BAD Protected High Impedance High Impedance (3-state) Table 5. Undervoltage Lockout 5V and VRXD Device (SN65HVD256) VCC VRXD DEVICE STATE BUS OUTPUT RXD GOOD GOOD Normal Per Device State and TXD Mirrors Bus BAD GOOD Protected High Impedance High (Recessive) GOOD BAD Protected Recessive High Impedance (3-state) BAD BAD Protected High Impedance High Impedance (3-state) APPLICATION NOTE: After an undervoltage condition is cleared and the supplies have returned to valid levels, the device typically resumes normal operation in 300 µs. FAULT Pin (SN65HVD257) If one or more of the faults (TXD-Dominant Timeout, RXD dominant Timeout, Thermal Shutdown or Undervoltage Lockout) occurs, the FAULT pin (open-drain) turns off, resulting in a high level when externally pulled up to VCC or IO supply. Figure 5. FAULT Pin Function Diagram and Application 6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SN65HVD255 SN65HVD256 SN65HVD257 |
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