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PCA9548ADBRG4 Datasheet(PDF) 8 Page - Texas Instruments

Part # PCA9548ADBRG4
Description  8-CHANNEL I2C SWITCH WITH RESET
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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PCA9548ADBRG4 Datasheet(HTML) 8 Page - Texas Instruments

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Power-On Reset
Voltage Translation
V
(V)
CC
2
1
1.5
4.5
3.5
2.5
5
4
3
2
2.5
3
3.5
4
4.5
5
5.5
Typical
Maximum
Minimum
I
=
100
A
SWout
-
m
Bus Transactions
Writes
PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
SCPS143C – OCTOBER 2006 – REVISED JUNE 2007
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9548A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9548A registers and I
2C
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up
to the operating voltage for a power-reset cycle.
The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another. Figure 6 shows the voltage characteristics of the
pass-gate transistors (note that the graph was generated using the data specified in the Electrical
Characteristics section of this data sheet).
Figure 6. Pass-Gate Voltage vs Supply Voltage at Three Process Points
For the PCA9548A to act as a voltage translator, the Vo(sw) voltage must be equal to, or lower than, the lowest
bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V,
Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in
Figure 6, Vo(sw)(max) is 2.7 V when the PCA9548A supply voltage is 3.5 V or lower, so the PCA9548A supply
voltage can be set to 3.3 V. Pullup resistors then can be used to bring the bus voltages to their appropriate
levels (see Figure 11).
Data is exchanged between the master and PCA9548A through write and read commands.
Data is transmitted to the PCA9548A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
SCn/SDn channel receives the data that follows the command byte (see Figure 7). There is no limitation on the
number of data bytes sent in one write transmission.
8
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Not Recommended For New Designs


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