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NM24W16UM8 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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NM24W16UM8 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 13 page 10 www.fairchildsemi.com NM24C16U/17U Rev. B.1 Write Operations BYTE WRITE For a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. Upon receipt of the byte address the NM24C16U/17U responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM24C16U/17U begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the NM24C16U/17U inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 6 for the address, acknowledge and data transfer sequence. PAGE WRITE The NM24C16U/17U is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. After the receipt of each byte, the NM24C16U/17U will respond with an acknowledge. After the receipt of each byte, the internal address counter increments to the next address and the next SDA data is accepted. If the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 7 for the address, acknowl- edge, and data transfer sequence. S T O P Bus Activity: Master SDA Line Bus Activity: NM24C16U/17U DATA n + 15 DATA n + 1 DATA n WORD ADDRESS (n) A C K S T A R T SLAVE ADDRESS A C K A C K A C K A C K S T O P A C K DATA A C K A C K S T A R T WORD ADDRESS SLAVE ADDRESS Bus Activity: Master SDA Line Bus Activity: NM24C16U/17U DS800010-15 DS800010-16 Acknowledge Polling Once the stop condition is issued to indicate the end of the host’s write operation the NM24C16U/17U initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM24C16U/17U is still busy with the write operation no ACK will be returned. If the NM24C16U/17U has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. Write Protection (NM24C17U Only) Programming of the upper half of the memory will not take place if the WP pin of the NM24C17U is connected to VCC. The NM24C17U will accept slave and byte addresses; but if the memory accessed is write protected by the WP pin, the NM24C17U will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. Byte Write (Figure 6) Page Write (Figure 7) |
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