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RC5054 Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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RC5054 Datasheet(HTML) 7 Page - Fairchild Semiconductor |
7 / 13 page PRODUCT SPECIFICATION RC5054A 7 Typical Application +12V +VOUT PGND RC5054 VSEN RT FB COMP VID0 VID1 VID2 VID3 SS PGOOD D/A GND OSC LGATE UGATE OCSET PHASE BOOT EN VCC VIN = +5V OVP MONITOR AND PROTECTION + - + - VID4 Applications Discussion Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These intercon- necting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 3 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board The components shown in Figure 3 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the RC5054A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the RC5054A must be sized to handle up to 1A peak current. Figure 3. Printed Circuit Board Power and Ground Planes or Islands Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, CSS close to the SS pin because the internal current source is only 10 µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. Figure 4. Printed Circuit Board Small Signal Layout Guidelines Feedback Compensation Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). PGND LO CO LGATE UGATE PHASE Q1 Q2 D2 VIN VOUT RETURN RC5054A CIN +12V RC5054A SS GND VCC BOOT D1 LO CO VOUT Q1 Q2 PHASE +VIN CBOOT CVCC CSS |
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