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AD7894BR-3 Datasheet(PDF) 8 Page - Analog Devices |
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AD7894BR-3 Datasheet(HTML) 8 Page - Analog Devices |
8 / 12 page AD7894 –8– REV. 0 250ns MIN BUSY SCLK CONVST CONVERSION IS INITIATED; TRACK/HOLD GOES INTO HOLD CONVERSION ENDS 10 s LATER SERIAL READ OPERATION READ OPERATION SHOULD END 250ns PRIOR TO NEXT RISING EDGE OF CONVST OUTPUT SERIAL SHIFT REGISTER IS RESET tCONVERT = 10 s PART WAKES UP Figure 4. Mode 2 Timing Diagram Where Automatic Sleep Function is Initiated t2 t3 t4 t5 t6 2 LEADING ZEROS THREE-STATE THREE- STATE 1 2 3 4 15 16 DB13 DB12 DB0 SCLK (I/P) DOUT (O/P) t2 = t3 = 31.25ns MIN, t4 = 60ns MAX, t5 = 10ns MIN, t6 = 20ns MAX @ 5V, A, B, VERSIONS Figure 5. Data Read Operation Mode 2 Operation (Auto Sleep After Conversion) The timing diagram in Figure 4 is for optimum performance in operating Mode 2, where the part automatically goes into sleep mode once BUSY goes low, after conversion and “wakes up” before the next conversion takes place. This is achieved by keep- ing CONVST low at the end of conversion, whereas it was high at the end of conversion for Mode 1 Operation. The rising edge of CONVST “wakes up” the AD7894. This wake-up time is typically 5 µs and is controlled internally by a monostable cir- cuit. While the AD7894 is waking up there is some digital activ- ity internal to the part. If the falling edge of CONVST (putting the track/hold amplifier into hold mode) should occur during this digital activity, noise will be injected into the track/hold amplifier resulting in a poor conversion. For optimum results the CONVST pulse should be between 40 ns and 2 µs or greater than 6 µs in width. The narrower pulse will allow a system to instruct the AD7894 to begin waking up and perform a conver- sion when ready, whereas the pulse greater than 6 µs will give control over when the sampling instant takes place. Note that the 10 µs wake-up time shown in Figure 4 is for a CONVST pulse less than 2 µs. If a CONVST pulse greater than 6 µs is used, the conversion will not complete for a further 5 µs after the falling edge of CONVST. Even though the part is in sleep mode, data can still be read from it. The read operation consists of 16 clock cycles as in Mode 1 Operation. For the fastest serial clock of 16 MHz, the read operation will take 1.0 µs and this must be complete at least 250 ns before the falling edge of the next CONVST, to allow the track/ hold amplifier to have enough time to settle. This mode is very useful when the part is converting at a slow rate, as the power consumption will be significantly reduced from that of Mode 1 Operation. Serial Interface The serial interface to the AD7894 consists of just three wires, a serial clock input (SCLK) and the serial data output (SDATA) and a conversion status output (BUSY). This allows for an easy-to-use interface to most microcontrollers, DSP processors and shift registers. Figure 5 shows the timing diagram for the read operation to the AD7894. The serial clock input (SCLK) provides the clock source for the serial interface. Serial data is clocked out from the SDATA line on the falling edge of this clock and is valid on both the rising and falling edges of SCLK. The advantage of having the data valid on both the rising and falling edges of the SCLK is to give the user greater flexibility in interfacing to the part and so a wider range of microprocessor and microcontrol- ler interfaces can be accommodated. This also explains the two timing figures, t4 and t5, that are quoted on the diagram. The time t4 specifies how long after the falling edge of the SCLK the next data bit becomes valid, whereas the time t5 specifies for how long after the falling edge of the SCLK the current data bit is valid. The first leading zero is clocked out on the first rising edge of SCLK. Note that the first zero will be valid on the first falling edge of SCLK even though the data access time is speci- fied at 60 ns for the other bits. The reason for this is that the first bit will be clocked out faster than the other bits is due to the internal architecture of the part. Sixteen clock pulses must be provided to the part to access to full conversion result. The AD7894 provides two leading zeros followed by the 14-bit conversion result starting with the MSB (DB13). The last data bit to be clocked out on the penultimate falling clock edge is the LSB (DB0). On the 16th falling edge of SCLK the LSB (DB0) will be valid for a specified time to allow the bit to be read on the falling edge of the SCLK and then the SDATA line is dis- abled (three-stated). After this last bit has been clocked out, the SCLK input should return low and remain low until the next serial data read operation. If there are extra clock pulses after the 16th clock, the AD7894 will start over again with outputting data from its output register and the data bus will no longer be three-stated even when the clock stops. Provided the serial clock has stopped before the next falling edge of |
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