©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013

Bel Fuse Inc.

206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com

7

Powerline Modules

Low Power Embedded HomePlug® AV Modules

MII Signals

Pin

Number

Pin Name

I/O

Description

MAC

Mode

PHY

Mode

30

31

32

33

MRX_D0

MRX_D1

MRX_D2

MRX_D3

I

O

MII Receive Data. The PHY controller drives MRX_D[3:0] and the

MAC core receives MRX_D[3:0]. MRX_D[3:0] transitions

synchronously with respect to MRX_CLK. For each MRX_CLK period

in which MRX_DV is asserted, MRX_D[3:0] is valid. MRX_D0 is the

least-significant bit. The PHY controller tri-states MRX_D[3:0] in isolate

mode.

34

COL

I

O

MII Collision Detected. The PHY controller asserts COL when it

detects a collision on the medium. COL remains asserted while the

collision condition persists. COL signal transitions are not synchronous

to either the MTX_CLK or the MRX_CLK. The MAC core ignores the

COL signal when operating in the full-duplex mode. The PHY

controller tristates COL in isolate mode.

35

MRX_CLK

I

O

MII Receive Clock. MRX_CLK is a continuous clock that provides the

timing reference for the transfer of the MRX_DV and MRX_D[3:0]

signals from the PHY controller to the MAC core. The PHY controller

sources MRX_CLK. MRX_CLK frequency is equal to 25% of the data

rate of the received signal on the Ethernet cable. The PHY controller

tri-states MRX_CLK in isolate mode.

37

MRX_ERR

I

O

MII Receive Error. The PHY controller asserts MRX_ERR high for

one or more MRX_ CLK periods to indicate to the MAC core that an

error (a coding error or any error that the PHY is capable of detecting

that is otherwise undetectable by the MAC) was detected somewhere

in the current frame. MRX_ERR transitions synchronously with respect

to MRX_CLK. While MRX_DV is de-asserted, MRX_ERR has no

effect on the MAC core. The PHY controller tri-states MRX_ERR in

isolate mode.

38

MRX_DV

I

O

MII Receive Data Valid. The PHY controller asserts MRX_DV to

indicate to the MAC core that it is presenting the recovered and

decoded data bits on MRX_D[3:0] and that the data on MRX_D[3:0] is

synchronous to MRX_CLK. MRX_DV transitions synchronously with

respect to MRX_CLK. MRX_DV remains asserted continuously from

the first recovered nibble of the frame through the final recovered

nibble, and is de-asserted prior to the first MRX_CLK that follows the

final nibble. The PHY controller tri-states MRX_DV in isolate mode.

39

MTX_D0

O

I

MII Transmit Data. The MAC core drives MTX_D[3:0] and the PHY

controller receives MTX_D[3:0]. MTX_D[3:0] transitions synchronously

with respect to MTX_CLK. For each MTX_CLK period in which

MTX_EN is asserted, MTX_D[3:0] is valid. MTX_D0 is the least

significant bit. The PHY controller ignores MTX_D[3:0] in isolate mode.

40

MTX_D1

41

MTX_D2

42

MTX_D3

43

CRS

I

O

MII Carrier Sense. The PHY controller asserts CRS when either

transmit or receive medium is non-idle. The PHY de-asserts CRS

when both transmit and receive medium are idle. The PHY must

ensure that CRS remains asserted throughout the duration of a

collision condition. The transitions on the CRS signal are not

synchronous to either the MTX_CLK or the MRX_CLK. The PHY

controller tri-states CRS in isolate mode.