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SN65LVDT101 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LVDT101 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 25 page  www.ti.com 50 Ω VOY VOZ 50 Ω VOD + - VCC - 2V + - 1.4 V 1 V tPLH 0.4 V 0 V VIA VIB VID 80% 100% 0% tPHL 20% tf tr VOD 0 V Y Z A B VID 1 pF VIB VIA VOD 100 Ω -0.4 V 50 Ω 50 Ω VCC - 2V + - OR VOD 0 V CLOCK INPUT 1/fo IDEAL OUTPUT 0 V 1/fo ACTUAL OUTPUT 0 V tc(n) 0 V PRBS INPUT 0 V ACTUAL OUTPUT 0 V PRBS OUTPUT Period Jitter Cycle to Cycle Jitter tjit(per) = |tc(n) - 1/fo| tc(n) tc(n+1) tjit(cc) = |tc(n) - tc(n+1)| tjit(pp) SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 SLLS516C – AUGUST 2002 – REVISED JUNE 2004 Figure 4. Typical Termination for LVPECL Output Driver (65LVDx101) NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. C L includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Measurement equipment provides a bandwidth of 5 GHz minimum. Figure 5. Timing Test Circuit and Waveforms Figure 6. Driver Jitter Measurement Waveforms 6 |
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