DS32EL0421 datasheet(7/32 Pages) TI1

Part #	DS32EL0421

Description	5-bit DDR LVDS Parallel Data Interface

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Manufacturer	TI1 [Texas Instruments]

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DS32EL0421, DS32ELX0421

www.ti.com

SNLS282F – MAY 2008 – REVISED APRIL 2013

SMBus Timing Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

tSMB

Bus Operating Frequency

10

100

kHz

tBUF

Bus Free Time between Stop and Start Condition

4.7

μs

tHD:STA

Hold time after (repeated) start condition. After this

4.0

μs

period, the first clock is generated.

tSU:STA

Repeated Start Condition Setup Time

4.7

μs

tSU:STO

Stop Condition Setup Time

4.0

μs

tHD:DAT

Data Hold Time

300

ns

tSU:DAT

Data Setup Time

250

ns

tLOW

Clock Low Time

4.7

μs

tHIGH

Clock High Time

4.0

50

μs

tF

Clock/Data Fall Time

20% to 80%

300

ns

tR

Clock/Data Rise Time

1000

ns

tSU:CS

SMB_CS Setup Time

30

ns

tPOR

Time in which the device must be operation after

See (3)

500

ms

power on

(1)

The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2)

Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions

at the time of product characterization and are not ensured.

(3)

Parameter is ensured by characterization and is not tested at production.

LVDS Electrical Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

VTH

Differential Input High Threshold

+100

mV

0.05V < VLVCM < VDD25 – 0.05V

VTL

Differential Input Low Threshold

-100

mV

VLVCM

LVDS Input Common Mode Voltage

0.05

VDD25 –

V

0.05

VLVOS

LVDS Input Loss of Signal

LVDS input loss of signal level.

20

mVP-P

See (4)

RLVIN

Input Impedance

Internal LVDS input termination

85

100

115

Ω

between differential pairs.

(1)

The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2)

Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

except VOD and ΔVOD.

(3)

Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions

at the time of product characterization and are not ensured.

(4)

If input LVDS signal is below 20mVP-P, loss of signal (LOS) is detected. The device will flag a valid input signal if the signal level is

above 100mVP-P

LVDS Timing Specifications

Over recommended operating supply and temperature ranges unless otherwise specified.

(1) (2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

f

Input DDR Clock (TxCLKIN) Frequency Range

125

312.5

MHz

tCIP

TxCLKIN Period

See Figure 3

3.2

2T

8

ns

(1)

The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2)

Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions

at the time of product characterization and are not ensured.

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