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GND

GND

ENA

ENA

NC

NC

NC

ENB

ENB

NC

NC

NC

GND

GND

A

B

NC

ENC

ENC

S0

S1

SM

END

END

GND

GND

A1Y

A1Z

A2Y

A2Z

A3Y

A3Z

A4Y

A4Z

B1Y

B1Z

B2Y

B2Z

B3Y

B3Z

B4Y

B4Z

C1Y

C1Z

C2Y

C2Z

C3Y

C3Z

C4Y

C4Z

D1Y

D1Z

D2Y

D2Z

D3Y

D3Z

D4Y

D4Z

DGG PACKAGE

(TOP VIEW)

SN65LVDS116

SLLS370D – SEPTEMBER 1999 – REVISED FEBRUARY 2005

16-PORT LVDS REPEATER

The intended application of this device and signaling

technique is for point-to-point or multidrop baseband

•

One Receiver and Sixteen Line Drivers Meet

data transmission over controlled impedance media

or Exceed the Requirements of ANSI

of approximately 100

Ω. The transmission media may

EIA/TIA-644 Standard

be printed-circuit board traces, backplanes, or cables.

•

Typical Data Signaling Rates to 400 Mbps or

The large number of drivers integrated into the same

Clock Frequencies to 400 MHz

substrate along with the low pulse skew of balanced

signaling, allows extremely precise timing alignment

•

Enabling Logic Allows Separate Control of

of the signals repeated from the input. This is

Each Bank of Four Channels or 2-Bit

particularly advantageous in system clock distribution.

Selection of Any One of the Four Banks

The SN65LVDS116 is characterised for operation

•

Low-Voltage Differential Signaling With

from –40

°C to 85°C.

Typical Output Voltage of 350 mV and a 100-

Ω

Load

•

Electrically Compatible With LVDS, PECL,

LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,

SSTL, or HSTL Outputs With External

Termination Networks

•

Propagation Delay Times < 4.7 ns

•

Output Skew Is < 300 ps and Part-to-Part

Skew < 1.5 ns

•

Total Power Dissipation Typically 470 mW

With All Ports Enabled and at 200 MHz

•

Driver Outputs or Receiver Input Is High

V

•

Bus-Pin ESD Protection Exceeds 12 kV

•

Packaged in Thin Shrink Small-Outline

Package With 20-Mil Terminal Pitch

The SN65LVDS116 is one differential line receiver

connected to sixteen differential line drivers that

implement the electrical characteristics of low-voltage

differential signaling (LVDS). LVDS, as specified in

EIA/TIA-644, is a data signaling technique that offers

the low-power, low-noise coupling, and fast switching

speeds to transmit data at relatively long distances.

(Note: The ultimate rate and distance of data transfer

is dependent upon the attenuation characteristics of

the media, the noise coupling to the environment, and

other system characteristics.)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1999–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.