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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

SN74GTL1655

16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER

WITH LIVE INSERTION

SCBS696I – JULY 1997 – REVISED APRIL 2005

This device is partitioned uniquely as two 8-bit transceivers with individual latch timing and output signals, but

with a common clock and output enable inputs for both transceiver words.

Data flow for each word is determined by the respective latch enables (LEAB and LEBA), output enables (OEAB

and OEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control byte 1 and

byte 2 data for the A-to-B and B-to-A directions, respectively.

For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions

low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK

low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the

high-impedance state.

Data flow for the B-to-A direction is identical, but uses OEBA, LEBA, and CLK. Note that CLK is common to both

directions and both 8-bit words. OE also is common and is used to disable all I/O ports simultaneously.

adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading conditions.

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power

connections, preventing disturbance of active data on the backplane during card insertion or removal, and

permits true live-insertion capability.

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown

resistors with the bus-hold circuitry is not recommended.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

TSSOP – DGG

Tape and reel

SN74GTL1655DGGR

GTL1655

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

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