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TAS5614APHDR Datasheet(PDF) 3 Page - Texas Instruments |
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TAS5614APHDR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 33 page  TAS5614A www.ti.com SLAS712B – JUNE 2010 – REVISED MARCH 2011 MODE SELECTION PINS MODE PINS OUTPUT PWM INPUT(1) DESCRIPTION CONFIGURATION M3 M2 M1 0 0 0 2N 2 × BTL AD mode 0 0 1 — — Reserved 0 1 0 2N 2 × BTL BD mode 0 1 1 1N 1 × BTL +2 ×SE AD mode 1 0 0 1N 4 × SE AD mode INPUT_C(2) INPUT_D(2) 2N 1 0 1 1 × PBTL 0 0 AD mode 1N 1 0 BD mode 1 1 0 Reserved 1 1 1 (1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode. (2) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode PACKAGE HEAT DISSIPATION RATINGS(1) PARAMETER TAS5614APHD TAS5614ADKD RθJC (°C/W) – 2 BTL or 4 SE channels 3.2 2.1 RθJC (°C/W) – 1 BTL or 2 SE channel(s) 5.4 3.5 RθJC (°C/W) – 1 SE channel 7.9 5.1 Pad Area (2) 64mm2 80mm2 (1) JC is junction-to-case, CH is case-to-heat sink (2) RθCH is an important consideration. Assume a 2-mil thickness of thermal grease with a thermal conductivity of 2.5 W/mK between the pad area and the heat sink and both channels active. The RθCH with this condition is 1.1°C/W for the PHD package and 0.44°C/W for the DKD package. Table 1. ORDERING INFORMATION(1) TA PACKAGE DESCRIPTION 0 °C–70°C TAS5614APHD 64 pin HTQFP 0 °C–70°C TAS5614ADKD 44 pin PSOP3 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TAS5614A |
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