TMS27C512 65536 BY 8BIT UV ERASABLE

TMS27PC512 65536 BY 8BIT

PROGRAMMABLE READONLY MEMORIES

SMLS512G − NOVEMBER 1985 − REVISED SEPTEMBER 1997

10

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

A0 − A15

E

Addresses Valid

ta(E)

G /VPP

DQ0 − DQ7

Hi-Z

ten(G)

tv(A)

tdis

Output Valid

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

Hi-Z

ta(A)

Figure 3. Read-Cycle Timing

A0 − A15

DQ0 − DQ7

G /VPP

VCC

Address Stable

VIH

VIL

VIH / VOH

VIL / VOL

VPP

VIL

VCC‡

VCC

tsu(A)

th(A)

tsu(D)

tsu(VPP)

tsu(VCC)

th(D)

tw(IPGM)

tdis(G)†

E

VIH

VIL

th(VPP)

Data-Out Valid

Hi-Z

Data-In Stable

tEHD

tr(PG)G

trec(PG)

† tdis(G) is a characteristic of the device but must be accommodated by the programmer.

‡ 13-V G /VPP and 6.5-V VCC for SNAP! Pulse programming.

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)