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AT45DB021E-SSHN-Y Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part # AT45DB021E-SSHN-Y
Description  2-Mbit DataFlash (with Extra 64-Kbits), 1.65V Minimum SPI Serial Flash Memory
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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AT45DB021E-SSHN-Y Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

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AT45DB021E
8789E–DFLASH–10/2013
Description
The Adesto® AT45DB021E is a 1.65V minimum, serial-interface sequential access Flash memory is ideally suited for a
wide variety of digital voice, image, program code, and data storage applications. The AT45DB021E also supports the
RapidS serial interface for applications requiring very high speed operation. Its 2,162,688 bits of memory are organized
as 1,024 pages of 256 bytes or 264 bytes each. In addition to the main memory, AT45DB021E also contains one SRAM
buffer of 256/264 bytes. The Buffer can be used as additional system scratch memory, and E2PROM emulation
(bit or byte alterability) can be easily handled with a self-contained three step read-modify-write operation.
Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the
Adesto DataFlash® uses a serial interface to sequentially access its data. The simple sequential access dramatically
reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise,
and reduces package size. The device is optimized for use in many commercial and industrial applications where
high-density, low-pin count, low-voltage, and low-power are essential.
To allow for simple in-system re-programmability, AT45DB021E does not require high input voltages for programming.
The device operates from a single 1.65V to 3.6V power supply for the erase and program and read operations. The
AT45DB021E is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial
Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
1.
Pin Configurations and Pinouts
Figure 1-1. Pinouts
Note:
1. The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.
This pad can be a “no connect” or connected to GND.
1
2
3
4
8
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
8-lead SOIC
Top View
SI
SCK
RESET
CS
SO
GND
VCC
WP
8
7
6
5
1
2
3
4
8-pad UDFN
Top View
SCK
GND
VCC
WP
NC
CS
SO
SI
RST
9-ball UBGA
Top View


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