74AUP1G3208

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 5 — 22 June 2012

3 of 19

NXP Semiconductors

74AUP1G3208

Low-power 3-input OR-AND gate

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level.

Fig 2.

Pin configuration SOT363

Fig 3.

Pin configuration SOT886

Fig 4.

Pin configuration SOT891,

SOT1115 and SOT1202

74AUP1G3208

AC

GND

BY

001aad500

1

2

3

6

5

4

74AUP1G3208

GND

001aad507

A

B

C

Y

Transparent top view

2

3

1

5

4

6

74AUP1G3208

GND

001aad506

A

B

C

Y

Transparent top view

2

3

1

5

4

6

Table 3.

Pin description

Symbol

Pin

Description

A

1

data input A

GND

2

ground (0 V)

B

3

data input B

Y

4

data output Y

5

supply voltage

C

6

data input C

Table 4.

Function table[1]

Input

Output

C

B

A

Y

LL

LL

LL

H

L

LH

LL

LH

H

L

HL

L

L

HL

HH

HH

L

H

HH

HH