TLV1572IDR datasheet(5/15 Pages) TI1

Part #	TLV1572IDR

Description	SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN

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Manufacturer	TI1 [Texas Instruments]

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TLV1572

2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN

SLAS171A – DECEMBER 1997– REVISED SEPTEMBER 1998

5

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, VCC = 5 V,

VREF = 5 V, fSCLK = 20 MHz (unless otherwise noted) (continued)

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Signal-to-noise ratio + distortion

f(input) = 200 kHz

54

58

dB

THD

Total harmonic distortion

f(input) = 200 kHz

56

60

dB

Effective number of bits

f(input) = 200 kHz

8.7

9.35

Bits

Spurious-free dynamic range

f(input) = 200 kHz

57

62

dB

Analog Input

BW

Full-power bandwidth

Source impedance = 1 k

Ω

12

MHz

BW

Small-signal bandwidth

Source impedance = 1 k

Ω

20

Mhz

timing specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tc

SCLK period

VCC = 4.5 V – 5.5 V

50

ns

tc

SCLK period

VCC = 2.7 V – 3.3 V

100

ns

trs

Reset and sampling period

6

SLCK

cycles

tc

Conversion period

10

SLCK

cycles

tsu1

FS setup time to SCLK falling edge in DSP mode

10

ns

th1

FS hold time to SCLK falling edge in DSP mode

4

ns

tsu2

FS setup time to CS falling edge in DSP mode

6

ns

th2

FS hold time to CS falling edge in DSP mode

9

ns

td1

Output delay after SCLK rising edge in DSP mode

15

25

ns

td(L)1

FS falling edge to next SCLK falling edge in DSP mode

6

ns

td(L)2

SCLK rising edge after CS falling edge in

µC mode

4

ns

td2

Output delay after SCLK rising edge in

µC mode

15

25

ns

Specifications subject to change without notice.

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