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TPS40130RHBR Datasheet(PDF) 11 Page - Texas Instruments |
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TPS40130RHBR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 39 page www.ti.com Current Sensing and Balancing (U1, U9 and U18) PowerGood 15 18 + + TPS40130DBT 0.616 V 0.784 V FB PGOOD PGOOD window comparator Optional components for hysteresis VOUT VPU RA CA RBIAS 10 k Ω 10 k Ω UDG−05078 R A + RBIAS V PU * VFB 1.3 0.16 V FB * 1 (1) TPS40130 SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 FUNCTIONAL DESCRIPTION (continued) The controller employs peak current mode control scheme, thus naturally provides certain degree of current balancing. With current mode, the level of current feedback should comply with certain guidelines depending on duty factor known as “slope compensation” to avoid the sub-harmonic instability. This requirement can prohibit achieving a higher degree of phase current balance. To avoid the controversy, a separate current loop that forces phase currents to match is added to the proprietary control scheme. This effectively provides high degree of current sharing independent of the controller’s small signal response and is implemented in U9, ICTLR. High bandwidth current amplifiers, U1 and U18 can accept as an input voltage either the voltage drop across dedicated precise current sense resistors, or inductor’s DCR voltage derived by an RC network, or thermally compensated voltage derived from the inductor’s DCR. The wide range of current sense arrangements ease the cost/complexity constrains and provides superior performance compared to controllers utilizing the low-side MOSFET current sensing. The current sense amplifier inputs must not exceed 4 V. See the Inductor DCR Current Sense section for more information on selecting component values for the R-C network. The PGOOD pin indicates when the inputs and output are within their specified ranges of operation. Also monitored are the EN/SYNC and SS pins. PGOOD has high impedance when indicating inputs and outputs are within specified limits and is pulled low to indicate an out-of-limits condition. Some applications may require hysteresis on the PGOOD signal to avoid a PGOOD signal bounce. A simple method to achieve this (and thereby eliminate any PGOOD signal bounce) is to add a small resistor (RA) and capacitor (CA) between the FB pin and the PGOOD pin. See Figure 3 for implementation. Figure 3. Adding Hysteresis to the PGOOD Signal To select RA and CA, the following criteria can be used. VPU and the PGOOD pull-up voltage and VFB is the TPS40130 internal reference voltage. The factor 1.3 in Equation 1 provides a margin for robustness. 11 Submit Documentation Feedback |
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