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TPS40130RHBT Datasheet(PDF) 5 Page - Texas Instruments |
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TPS40130RHBT Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 39 page  www.ti.com TPS40130 SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) T A = -40°C to 85°C, VIN = 12 V, RRT = 64.9 kΩ, TJ = TA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SOFT START 32 clocks after EN/SYNC before SS current ISS Soft-start source current 3.5 5.0 6.5 µA begins VSS Fault enable threshold voltage 0.95 1.00 1.05 V CURRENT SENSE AMPLIFIER Input offset voltage CS1, CS2 -5 4 10 mV Gain transfer to PWM comparator -100 mV ≤ V CS≤ 100 mV, VCSRT = 1.5 V 5.1 5.6 6.1 V/V Transconductance to DROOP VCS - VCSRTn = 100 mV 40 µA Gain variance between phases VCS - VCSRTn = 100 mV -4% 0 4% Input offset variance VCS = 0 V -3.5 0 3.5 mV Offset current at DROOP VCS - VCSRTn = 0 V 6 µA Input common mode (2) 0 VBP5-0.7 V Bandwidth(2) 18 MHz DIFFERENTIAL AMPLIFIER Gain 1 V/V Gain tolerance VOUT = 4 V vs VOUT = 0.7 V, VGSNS = 0 V -0.5% 0.5% CMRR Common mode rejection ratio(2) 0.7 V ≤ V OUT ≤ 4.0 V 60 dB Output source current VOUT - VGSNS = 2.0 V, VDIFFO≥ 1.98 V 2 4 mA Output sink current VOUT - VGSNS = 2.0 V, VDIFFO≥ 2.02 V 2 4 Input offset voltage(2) 0.7 V ≤ V OUT ≤ 4.0 V 5 mV Bandwidth(2) 5 MHz Input impedance, non-inverting(2) VOUT to GND 40 k Ω Input impedance, inverting(2) VGSNS to VDIFFO 40 GATE DRIVERS Source on-resistance, HDRV1, VBOOT1 = 5 V, VBOOT2 = 5 V, VSW1 = 0 V, 1.0 2.0 3.5 HDRV2 VSW2 = 0 V, Sourcing 100 mA Ω VBOOT1 = 5 V, VBOOT2 = 5 V, VVIN5 = 5 V, Sink on-resistance, HDRV1, HDRV2 0.5 1.0 2.0 VSW1 = 0 V, VSW2 = 0 V, Sinking 100 mA Source on-resistance, LDRV1, VVIN5 = 5 V, VSW1 = 0 V, VSW2 = 0 V, 1 2 3.5 LDRV2 Sourcing 100 mA Ω VVIN5 = 5 V, VSW1 = 0 V, VSW2 = 0 V, Sink on-resistance, LDRV1, LDRV2 0.30 0.75 1.50 Sinking 100 mA tRISE Rise time, HDRV(2) CLOAD = 3.3 nF 25 75 tFALL Fall time, HDRV(2) CLOAD = 3.3 nF 25 75 tRISE Rise time, LDRV(2) CLOAD = 3.3 nF 25 75 tFALL Fall time, LDRV(2) CLOAD = 3.3 nF 25 60 ns SW falling to LDRV rising 50 tDEAD Dead time(2) LDRV falling to SW rising 30 tON Minimum controllable on-time(2) CLOAD = 3.3 nF 150 OUTPUT UNDERVOLTAGE FAULT VFB relative to GND 560 588 610 mV Undervoltage fault threshold VFB relative to VVREF -20% -16% -13% OUTPUT OVERVOLTAGE SET VOVSET relative to GND 796 817 832 mV Overvoltage threshold VOVSET relative to VVREF 14% 16% 19% (2) Ensured by design. Not production tested. 5 Submit Documentation Feedback |
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