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MAX6315US41D2-T Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX6315US41D2-T Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 7 page _______________Detailed Description Reset Output A microprocessor’s (µP’s) reset input starts the µP in a known state. The MAX6315 asserts reset to prevent code-execution errors during power-up, power- down, or brownout conditions. RESET is guaranteed to be a logic-low for VCC > 1V (see the Electrical Characteristics table). Once VCC exceeds the reset threshold, the internal timer keeps reset asserted for the reset timeout period (tRP); after this interval RESET goes high. If a brownout condition occurs (monitored voltage dips below its programmed reset threshold), RESET goes low. Any time VCC dips below the reset threshold, the internal timer resets to zero and RESET goes low. The internal timer starts when VCC returns above the reset threshold, and RESET remains low for the reset timeout period. The MAX6315’s RESET output structure is a simple open-drain n-channel MOSFET switch. Connect a pull- up resistor to any supply in the 0V to +6V range. Select a resistor value large enough to register a logic low when RESET is asserted (see the Electrical Characteristics table), and small enough to register a logic high while supplying all input current and leakage paths connected to the RESET line. A 10k Ω pullup is sufficient in most applications. Often, the pull-up connected to the MAX6315’s RESET output will connect to the supply voltage monitored at the IC’s VCC pin. However, some systems may use the open-drain output to level-shift from the monitored sup- ply to reset circuitry powered by some other supply (Figure 1). This is one useful feature of an open-drain output. Keep in mind that as the MAX6315’s VCC decreases below 1V, so does the IC’s ability to sink current at RESET. Finally, with any pullup, RESET will be pulled high as VCC decays toward 0V. The voltage where this occurs depends on the pull-up resistor value and the voltage to which it connects (see the Electrical Characteristics table). Manual-Reset Input Many µP-based products require manual-reset capa- bility, allowing the operator, a test technician, or exter- nal logic circuitry to initiate a reset. A logic low on MR asserts reset. Reset remains asserted while MR is low, and for the reset active timeout period after MR returns high. MR has an internal 63k Ω pullup resistor, so it can be left open if not used. Connect a normally open momen- tary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1µF capacitor from MR to ground provides additional noise immunity. __________Applications Information Negative-Going VCC Transients In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, these devices are relatively immune to short-duration negative-going transients (glitches). The Typical Operating Character- istics show the Maximum Transient Duration vs. Reset Threshold Overdrive, for which reset pulses are not generated. The graph was produced using negative- going pulses, starting at VRST max and ending below the programmed reset threshold by the magnitude indi- cated (reset threshold overdrive). The graph shows the maximum pulse width that a negative-going VCC tran- sient may typically have without causing a reset pulse to be issued. As the transient amplitude increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. A 0.1µF bypass capacitor mounted close to VCC provides additional transient immunity. Open-Drain SOT µP Reset Circuit 4 _______________________________________________________________________________________ Figure 1. MAX6315 Open-Drain RESET Output Allows Use with Multiple Supplies MAX6315 VCC GND RESET MR 5V SYSTEM +5.0V +3.3V 10k Ω |
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