bq4802Y

bq4802LY

SLUS464C – AUGUST 2000 – REVISED JUNE 2002

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10

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tF

VCC slew rate fall time

3.0 V to 0 V

300

tR

VCC slew rate rise time

100

t

Interrupt delay time from V

bq4802Y

6

24

s

tPF

Interrupt delay time from VPFD

bq4802LY

10

40

µs

t

Write protect time for external SRAM

bq4802Y

See Note 1

90

100

125

tWPT

Write-protect time for external SRAM

bq4802LY

See Note 1

150

170

210

t

CS at V

after power up

bq4802Y

See Note 2

100

200

300

tCSR

CS at VHI after power-up

bq4802LY

See Note 2

170

330

500

ms

tRST

VPFD to RST active (reset active time-out period)

tCSR

tCSR

ms

tCER

Device enable recovery time

See Note 3

tCSR

tCSR

t

Device enable propagation delay time to external SRAM

bq4802Y

Output load A

9

15

ns

tCED

Device enable propagation delay time to external SRAM

bq4802LY

Output load A

15

25

ns

tPBL

Push-button low time

1

µs

(1) Delay after VCC slews down past VPFD before SRAM is write protected and RST activated.

(2) Internal write-protection period after VCC passes VPFD on power up.

(3) Time during which external SRAM is write protected after VCC passes VPFD on power up.

CAUTION:NEGATIVE UNDERSHOOTS BELOW THE ABSOLUTE MAXIMUM RATING OF –0.3 V IN BATTERY-

BACKUP MODE MAY AFFECT DATA INTEGRITY.

VPFD

VCC

2.8

VCC

CS

RST

CEIN

CEOUT

INT

VPFD

tF

tFS

VSO

VSO

VPFD(max)

tR

tCSR

tCER

tCED

tCED

tPF

VOHB

High-Z

tRST

tWPT

NOTES: A. PWRIE set to 1 to enable power fail interrupt.

B. RST and INT are open drain and require and external pullup resistor.

Figure 9. Power-Down/Power-Up Timing Diagram