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SPT7710AIJ Datasheet(PDF) 6 Page - Fairchild Semiconductor |
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SPT7710AIJ Datasheet(HTML) 6 Page - Fairchild Semiconductor |
6 / 12 page 6 8/17/01 SPT7710 double-sided PC board with a ground plane on the compo- nent side separated into digital and analog sections will give the best performance. The converter is bonded-out to place the digital pins on the left side of the package and the analog pins on the right side. Additionally, an RF bead connection through a single point from the analog to digi- tal ground planes will reduce ground noise pickup. The circuit in figure 2 (PGA and cerquad packages only) is intended to show the most elaborate method of achieving the least error by correcting for integral nonlinearity, input induced distortion, and power supply/ground noise. This is achieved by the use of external reference ladder tap con- nections, an input buffer, and supply decoupling. The func- tion of each pin and external connections to other compo- nents is as follows: Figure 2 – Typical Interface Circuit 2 (PGA and Cerquad packages only) VEE VCC 10-25 W VR1 + .01 µF 256 to 8-Bit Encoder ECL Latches And Buffers VR2 VRTF LINV MINV VRBF Analog Input Force 2 V 2.2 µF 5.2 V Clock Buffer Preamp Comparator VEE AGND DGND VRTS VRBS 50 W DREAD DRINV Overrange D8 MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 AGND VEE AGND 5.2 V .01 µF .01 µF 2 Analog Input (Sense) .01 µF CLK CLK 100116 Convert 2 V (Digital) L 10-25 W VR3 + .01 µF 10-25 W + .01 µF VIN VIN 50 W 2 128 64 191 256 127 192 151 63 1 .01 µF 2 V (Analog) VEE U2 U2 U2 U1 and U2= Rail-to-Rail Op Amp D1=HP, 1N5712 Q1=1N2222A Q2=1N2907A R = 1 kW, .1% R R R R + U1 Voltage Limiter *See below RT 5.2 D1 D2 RS 49.9 Typical Voltage Limiter .01 µF + U1 22 10 W VCC Q1 D1 VEE 2 V VREF VEE + 22 W U2 .01 µF VEE, AGND, DGND VEE is the supply pin with AGND as ground for the device. The power supply pins should be bypassed as close to the device as possible with at least a .01 µF ceramic capaci- tor. A 1 µF tantalum should also be used for low frequency suppression. DGND is the ground for the ECL outputs and is to be referenced to the output pulldown voltage and appropriately bypassed as shown in figure 1. VIN (ANALOG INPUT) There are two analog input pins that are tied to the same point internally. Either one may be used as an analog input sense and the other for input force. This is convenient for testing the source signal to see if there is sufficient drive capability. The pins can also be tied together and driven by |
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