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TMS320DM640ZDK400 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320DM640ZDK400 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 179 page  Tables 11 June 2003 − Revised October 2010 SPRS222F Table Page 4−26 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module 113 . . . . . . . . . . . . . . . . . . . . . . 4−27 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM Cycles for EMIFA Module 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−28 Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module 119 . . . . . . . . . . . . . . . . . . . . . . . . 4−29 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA Cycles for EMIFA Module 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−30 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−31 McASP0 Control Registers 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−32 McASP0 Data Registers 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−33 Timing Requirements for McASP 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−34 Switching Characteristics Over Recommended Operating Conditions for McASP 126 . . . . . . . . . . . . . . . 4−35 I2C0 Registers 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−36 Timing Requirements for I2C Timings 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−37 Switching Characteristics for I2C Timings 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−38 HPI Registers [DM641 Only] 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−39 Timing Requirements for Host-Port Interface Cycles [DM641 Only] 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−40 Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles [DM641 Only] 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−41 McBSP 0 Registers 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−42 McBSP 1 Registers 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−43 Timing Requirements for McBSP 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−44 Switching Characteristics Over Recommended Operating Conditions for McBSP 140 . . . . . . . . . . . . . . . 4−45 Timing Requirements for FSR When GSYNC = 1 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−46 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 142 . . . . . . . . . . 4−47 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−48 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 143 . . . . . . . . . . 4−49 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−50 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 144 . . . . . . . . . . 4−51 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−52 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 145 . . . . . . . . . . 4−53 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−54 Video Port 0 and 1 (VP0 and VP1) Control Registers 146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−55 Timing Requirements for Video Capture Mode for VPxCLKINx 149 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−56 Timing Requirements in Video Capture Mode for Video Data and Control Inputs 150 . . . . . . . . . . . . . . . . 4−57 Timing Requirements for Video Display Mode for VPxCLKINx 151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−58 Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to VPxCLKINx and VPxCLKOUTx 151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−59 Switching Characteristics Over Recommended Operating Conditions in Video Display Mode for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx 152 . . . . . . 4−60 Timing Requirements for Dual-Display Sync Mode for VPxCLKINx 153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−61 VCXO Interpolated Control (VIC) Port Registers 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−62 Timing Requirments for STCLK 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−63 Ethernet MAC (EMAC) Control Registers 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−64 EMAC Statistics Registers 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−65 EMAC Wrapper 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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