UCC2946

UCC3946

SLUS247F − APRIL 1997 − REVISED NOVEMBER 2007

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APPLICATION INFORMATION

Once VDD rises above the programmed threshold, RES remains low for the reset period defined by:

T

C

RP

source of 400 nA, a high-quality, low-leakage capacitor (such as an NPO ceramic) should be used to maintain

timing tolerances. Figure 3 illustrates the voltage levels and timings associated with the reset circuit.

UDG−97067

t1: VDD > 1 V, RES is ensured low.

t2: VDD > programmed threshold, RES remains low for TRP.

t3: TRP expires, RES pulls high.

t4: Voltage glitch occurs, but is filtered at the RTH pin, RES remains high.

t5: Voltage glitch occurs whose magnitude and duration is greater than the RTH filter, RES is asserted for TRP.

t6: On completion of the TRP pulse the RTH voltage has returned and RES is pulled high.

t7: VDD dips below threshold (minus hysteresis), RES is asserted.

Figure 3. Reset Circuit Timings

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