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LT1317 Datasheet(PDF) 8 Page - Linear Technology |
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LT1317 Datasheet(HTML) 8 Page - Linear Technology |
8 / 16 page 8 LT1072 1072fc rough guide to calculate LT1072 power dissipation. For more details, the reader is referred to Application Note 19 (AN19), “Efficiency Calculations” section. Average supply current (including driver current) is: IIN ≈ 6mA + ISW(0.004 + DC/40) ISW = switch current DC = switch duty cycle Switch power dissipation is given by: PSW = (ISW)2 • RSW • DC RSW = LT1072 switch “on” resistance (1Ω maximum) Total power dissipation is the sum of supply current times input voltage plus switch power: PTOT = (llN)(VIN) + PSW In a typical example, using a boost converter to generate 12V @ 0.12A from a 5V input, duty cycle is approximately 60%, and switch current is about 0.65A, yielding: llN = 6mA + 0.65(0.004 + DC/40) = 18mA PSW = (0.65)2 • 1Ω • (0.6) = 0.25W PTOT = (5V)(0.018A) + 0.25 = 0.34W Temperature rise in a plastic miniDIP would be 130°C/W times 0.34W, or approximately 44°C. The maximum ambient temperature would be limited to 100°C (commercial temperature limit) minus 44°C, or 56°C. In most applications, full load current is used to calculate die temperature. However, if overload conditions must also be accounted for, four approaches are possible. First, if loss of regulated output is acceptable under overload conditions, the internal thermal limit of the LT1072 will protect the die in most applications by shutting off switch current. Thermal limit is not a tested parameter, however, and should be considered only for non-critical applications with temporary overloads. A second approach is to use the larger TO-220 (T) or TO-3 (K) package which, even without a heat sink, may limit die temperatures to safe levels under overload conditions. In critical situations, heat sinking of these packages is required; especially if overload conditions must be tolerated for extended periods of time. The third approach for lower current applications is to leave the second switch emitter open. This increases switch “on” resistance by 2:1, but reduces switch current limit by 2:1 also, resulting in a net 2:1 reduction in I2R switch dissipation under current limit conditions. The fourth approach is to clamp the VC pin to a voltage less than its internal clamp level of 2V. The LT1072 switch current limit is zero at approximately 1V on the VC pin and 2A at 2V on the VC pin. Peak switch current can be externally clamped between these two levels with a diode. See AN-19 for details. LT1072 Synchronizing The LT1072 can be externally synchronized in the frequency range of 48kHz to 70kHz. This is accomplished as shown in the accompanying figures. Synchronizing occurs when the VC pin is pulled to ground with an external transistor. To avoid disturbing the DC characteristics of the internal error amplifier, the width of the synchronizing pulse should be under 1µs. C2 sets the pulse width at ≈ 0.35µs. The effect of a synchronizing pulse on the LT1072 amplifier offset can be calculated from: KT = 26mV at 25°C q tS = pulse width fS = pulse frequency IC = LT1072 VC source current (≈ 200µA) VC = LT1072 operating VC voltage (1V to 2V) R3 = resistor used to set mid-frequency “zero” in LT1072 frequency compensation network. With tS = 0.35µs, fS = 50kHz, VC = 1.5V, and R3 = 2KΩ, offset voltage shift is ≈2.2mV. This is not particularly bothersome, but note that high offsets could result if R3 were reduced to a much lower value. Also, the synchronizing transistor must sink higher currents with low values of R3, so larger drives may have to be used. The transistor must be capable of pulling the VC pin to within 200mV of ground to ensure synchronizing. LT1072 OPERATIO ∆VOS = (tS)(fS) IC + IC KT q (( ( VC R3 ( |
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