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MAX11210 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX11210 Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 14 page 4 Maxim Integrated 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface MAX11202 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization. Note 3: VAINP = VAINN. Note 4: ppmFSR is parts per million of full-scale range. Note 5: Positive full-scale error includes zero-scale errors. Note 6: The MAX11202A has no normal-mode rejection at 50Hz or 60Hz. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Rising Edge Data Hold Time t4 Allows for positive edge data read 3 ns RDY/DOUT Fall to SCLK Rising Edge t5 0 ns Next Data Update Time; No Read Allowed t6 MAX11202A 155 F s MAX11202B 169 Data Conversion Time t7 MAX11202A 8.6 ms MAX11202B 73 Data Ready Time After Calibration Starts (CAL + CNV) t8 MAX11202A 208.3 ms MAX11202B 256.1 SCLK High After RDY/DOUT Goes Low to Activate Sleep Mode t9 MAX11202A 0 8.6 ms MAX11202B 0 73 Time from RDY/DOUT Low to SCLK High for Sleep-Mode Activation t10 MAX11202A 0 8.6 ms MAX11202B 0 73 Data Ready Time After Wake-Up from Sleep Mode t11 MAX11202A 8.6 ms MAX11202B 73 Data Ready Time After Calibration from Sleep Mode Wake-Up (CAL + CNV) t12 MAX11202A 208.4 ms MAX11202B 256.2 |
Similar Part No. - MAX11210 |
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Similar Description - MAX11210 |
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