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MAX11212AEUB Datasheet(PDF) 3 Page - Maxim Integrated Products |
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MAX11212AEUB Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 14 page 3 Maxim Integrated 18-Bit, Single-Channel, Ultra-Low Power, Delta- Sigma ADC with 2-Wire Serial Interface MAX11212 ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REF Input Capacitance 15 pF AIN Voltage Range VAINP - VAINN -VREF +VREF V REF Voltage Range VAVDD V Input Sampling Rate fS MAX11212A 246 kHz MAX11212B 225 REF Sampling Rate MAX11212A 246 kHz MAX11212B 225 LOGIC INPUTS (SCLK, CLK) Input Current Input leakage current ±1 F A Input Low Voltage VIL 0.3 x VDVDD V Input High Voltage VIH 0.7 x VDVDD V Input Hysteresis VHYS 200 mV External Clock MAX11212A 2.4576 MHz MAX11212B 2.2528 LOGIC OUTPUTS (RDY/DOUT) Output Low Level VOL IOL = 1mA; also tested for VDVDD = 3.6V 0.4 V Output High Level VOH IOH = 1mA; also tested for VDVDD = 3.6V 0.9 x VDVDD V Floating State Leakage Current Output leakage current ±10 F A Floating State Output Capacitance 9 pF POWER REQUIREMENTS Analog Supply Voltage AVDD 2.7 3.6 V Digital Supply Voltage DVDD 1.7 3.6 V Total Operating Current AVDD + DVDD 230 300 F A DVDD Operating Current 45 60 F A AVDD Operating Current 185 245 F A AVDD Sleep Current 0.4 2 F A DVDD Sleep Current 0.35 2 F A 2-WIRE SERIAL-INTERFACE TIMING CHARACTERISITCS SCLK Frequency fSCLK 5 MHz SCLK Pulse Width Low t1 60/40 duty cycle 5MHz clock 80 ns SCLK Pulse Width High t2 40/60 duty cycle 5MHz clock 80 ns SCLK Rising Edge to Data Valid Transition Time t3 40 ns |
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